CYUSB3KIT-003 PCLK voltage level?

KIMI_4749046 · ‎Sep 01, 2020

I use CYUSB3KIT-003 KIT

I want to connect CYUSB3KIT-003 and Ultrascale FPGA Board.

I set up GPIF Master and want to use some signal and PCLK.

I know CYUSB3KIT support 1.8v and 3.3v voltage levels. I want to use 1.8v signal level.

But J2 jumper is opend. the PCLK level is still 3.3v.

How can I use the pclk level is 1.8v. Please give me the idea.

Thanks.

Rashi_Vatsa · ‎Sep 03, 2020

Hello,

We modified the GPIF master firmware (AN87216).

>> Please share the modified GPIF master firmware (used for your application) so that we can try to reproduce the issue at our end

When transferring bulk data, the peak voltage of CTL signals are over 1.8v.

>> Please measure the voltage at VIO while transferring data and share the result

1) How can I get the 1.8v on PCLK?

>> 1.8 V is expected at PCLK with the J2 jumper removed. As mentioned earlier, we measured the 1.8 V at PCLK with the default GPIF master firmware

>> Please try measuring the PLCK (with J2 removed) after programming the FX3 with default firmware attached with the application note AN87216 https://www.cypress.com/documentation/application-notes/an87216-designing-gpif-ii-master-interface

2) In Superspeed Explorer Kit, page 4 CVDDQ is V3P3.

Is it related with PCLK 3.3V?

>> No, the PCLK pin doesn't fall under the CVDDQ power domain. Please refer to Table 7 of the FX3 datasheet for pins falling under the CVDDQ power domain.

Regards,

Rashi

Regards,
Rashi

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CYUSB3KIT-003 PCLK voltage level?

CYUSB3KIT-003 PCLK voltage level?

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