CYUSB3065 USB 3.0 Enumeration - power supply problems?

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ChTo_4134406
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Welcome!

Hi,

I'm developing a custom PCB with the CYUSB3065. I know questions regarding USB 3 enumeration have been asked many times, but I haven't been able to solve my problem so I need a bit more detail. At this stage I'm not really sure what the problem is, as I believe I have designed my board to the specifications, but happy to be proven wrong.

Problem description:

  • My custom PCB will enumerate as a USB 2.1 High Speed device, but not a USB 3.0 Superspeed device.
  • I believe this is a hardware issue because my PCB fails to enumerate when only running the example program cyfxbulksrcsink that comes with the EZ-USB FX3 SDK.

So far:

I think there is still a power supply issue - maybe caused by the inrush current event when the USB3.0 SuperSpeed PHY is enabled?

Question:

Is this too much noise?

See these three images. The red trace is the working Denebola CX3 board. The blue trace is my custom PCB. The green trace is a GPIO pin that is set just before USB 3.0 is enabled. I've attached the portion of code used to capture these images (USB-3-test.txt).

Custom-vs-Denebola-U3TXVDDQ.pngCustom-vs-Denebola-U3RXVDDQ.pngCustom-vs-Denebola-AVDD.png

On the blue traces (my custom PCB), for U3TXVDDQ and U3RXVDDQ, the minimum voltage is about 1.1V, and the peak is about 1.27V. This doesn't seem drastically greater than the red reference trace.

See also this - the 5V VBUS supply (in blue). There is a voltage drop of 500mV when USB 3.0 is enabled (from 5V down to 4.5V).

I can reduce this voltage drop to only 250mV by adding a large capacitor across VBUS, but doing that doesn't cause the board to magically enumerate.

VBUS.png

Is any of this noise likely to be the cause of my device failing to enumerate as USB 3.0?

Any help appreciated,

Thanks!

P.S. I've also attached pictures comparing my custom PCB power supplies with that of the the Denebola CX3 board (Supplies.zip). In all images my custom PCB is the yellow trace, and the Denebola board is the green trace. I captured both so I could be sure I wasn't seeing just the noise on my oscilloscope - it's clearly common to both boards. I'm pretty sure these supplies are within the stated 20 mV/100 mV spec.

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1 Solution
Rashi_Vatsa
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5 likes given 500 solutions authored 1000 replies posted

Hello,

As per the hardware check of this KBA Trouble Shooting Guide for the FX3/FX3S/CX3 Enumeration - KBA222372

- Clock source as per spec: Please let me know if the same clock source is used for CLKIN and REFCLK. If yes,  the clock must be passed through a buffer with two outputs and then connected to the clock pins. Please confirm.

- Range of U3TXVDDQ and U3RXVDDQ: As mentioned in the CX3 the datasheet, the range of these to power domain is

                                                                  min                 max

cx3_datasheet.PNG

The values measured on yous custom board is not in the range specified int the CX3 datasheet. The voltage on U3TXVDDQ and U3RXVDDQ should be between 1.15 - 1.25V. Please confirm that this spec is met on your custom board.

- You can refer to the shcematics of the reference desgin https://www.cypress.com/documentation/development-kitsboards/denebola-usb-30-uvc-reference-design-ki...

- From the debug prints it seems that USB type C is used in your design

If yes, please refer to this KBA for type C schematics Designing FX3™/CX3-Based USB Type-C Products - KBA218460

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi

View solution in original post

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3 Replies
Rashi_Vatsa
Moderator
Moderator
Moderator
5 likes given 500 solutions authored 1000 replies posted

Hello,

As per the hardware check of this KBA Trouble Shooting Guide for the FX3/FX3S/CX3 Enumeration - KBA222372

- Clock source as per spec: Please let me know if the same clock source is used for CLKIN and REFCLK. If yes,  the clock must be passed through a buffer with two outputs and then connected to the clock pins. Please confirm.

- Range of U3TXVDDQ and U3RXVDDQ: As mentioned in the CX3 the datasheet, the range of these to power domain is

                                                                  min                 max

cx3_datasheet.PNG

The values measured on yous custom board is not in the range specified int the CX3 datasheet. The voltage on U3TXVDDQ and U3RXVDDQ should be between 1.15 - 1.25V. Please confirm that this spec is met on your custom board.

- You can refer to the shcematics of the reference desgin https://www.cypress.com/documentation/development-kitsboards/denebola-usb-30-uvc-reference-design-ki...

- From the debug prints it seems that USB type C is used in your design

If yes, please refer to this KBA for type C schematics Designing FX3™/CX3-Based USB Type-C Products - KBA218460

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi
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Hi Rashi,

Thanks for the info.

  • I use a single clock source for both clk pins, and it is buffered. [Clock​​, Buffer​] A waveform of the clock, at the buffered output, can be seen in my previous attachment Supplies.zip
  • For U3TXVDDQ and U3RXVDDQ: The power supply is nominally 1.2V, but it does peak outside the limits for ~10us when USB 3.0 is enabled. As shown in the pics in the previous post, the minimum is 1.11V and the max is 1.27V. Can you confirm that this will cause a problem, even though the voltage peaks are brief (10us)?
  • Assuming that yes, this is a problem, can you provide specifications for an appropriate choke/ferrite bead to suppress these voltage peaks? I'm currently using the MPZ2012S601ATD25 ​(see pic snippet of power supplies).
    (The AN70707 Schematic Checklist mentions using a choke, but gives no specs.)pwr.PNG
  • My design is based off the reference schematic you linked https://www.cypress.com/documentation/development-kitsboards/denebola-usb-30-uvc-reference-design-ki...
  • My design uses USB 3 micro, not USB type-C. However, the SSRX P/N differential pair is inverted on my board to avoid changing layers

Thanks

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Hello,

- Can you confirm that this will cause a problem, even though the voltage peaks are brief (10us)?

>> As mentioned in the KBA Trouble Shooting Guide for the FX3/FX3S/CX3 Enumeration - KBA222372  we recommend that noise should on power supplies U3TXVDDQ, U3RXVDDQ, AVDD should be less than 20mV but in your design, the noise is quite high even if it is for 10us.

It is mentioned in section 4.3 of  AN70707, when the USB3.0 SuperSpeed PHY is enabled for the first time, or a reset event; an initial inrush current is expected on the 1.2 V U3RXVDDQ and U3TXVDDQ supplies for ~10 µs. The magnitude of this current can be as high as 800 mA. In order that this inrush current does not cause the common 1.2-V supply to drop to unacceptable levels, care must be taken in the design of the power supply network for these supplies.

So, we recommend reducing the noise levels below 20mV on the power supplies  (U3TXVDDQ, U3RXVDDQ, AVDD) in your design.

- can you provide specifications for an appropriate choke/ferrite bead to suppress these voltage peaks? I'm currently using the MPZ2012S601ATD25

>> You can refer to the ferrite beads and the LDO's used in the schematic of the FX3 SuperSpeed Explorer kit  https://www.cypress.com/documentation/development-kitsboards/cyusb3kit-003-ez-usb-fx3-superspeed-exp... or refer  Denebola kit's schematics

You can also refer to Appendix A of AN70707 for the tips to reduce the noise levels

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi
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