Hello,
If Watermark value of 2 is used in the firmware (16-bit data bus), then the FPGA must be able to write 2 data words after the assertion of Flag-B. After 5 cycles of assertion of Flag B, Flag A needs to be asserted (pulled low by the FX3 firmware). Is this condition is being met?
I see that the SLWR and Flag A is de-asserted. Please make sure that the entire DMA buffer is filled, i.e. SLWR is being asserted till 2 more data words are written after the assertion of Flag B. If this is not satisfied, then the DMA buffer is not filled and not committed to the USB side. This may be the cause for the issue.
Please refer to the Figure 13. in AN65974 for the waveform.
You can use a logic analyzer to probe the signals on the GPIF side and check if the SLWR is asserted only after completely filling the DMA buffer, else there will be no buffer committed to the USB side.
To check if the issue is from the firmware, you can continuously assert (pulled low) the SLCS, SLWR signal on the GPIF side, and stream IN the data using the streamer application.
If possible, can you please connect a Serial device to the UART lines of the FX3 to get the debug prints?
Thanks,
Yatheesh
