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USB Superspeed Peripherals

Stevenlm57
New Contributor

Dear Sir,

I designed a custom board with CY3014+FPGA for slavefifo stream-out function for printer purpose.

The config are : GPIF interface external PCLK 48Mhz,32bits,slave fifo out. 

While testing,all works OK but sometimes my PC side application(C) showed a problem of transfer failed,err code =997 and could not send data anymore,once close program and re-run ,and it could send again.Unstable.

I verified it by download USBBulkLoopAuto.img to cy3014 , and tested by Bulk Loop.exe for loopback test , no problem .like pictures attached.(sorry,I found I have no permission to upload images yet).

So,means PC->driver->usb 3.0 cable ->CY3014 chip loop back are all normal.

Then,I switched back to my slavefifo.img  and  run Cypress Streamer. 

At first,it worked fine,however, some minutes later, the receiving is stopped and the error message is "Xfer request rejected. NTSTATUS = c0000001".

The interface between CY3014 and FPGA are simple :

32bits data(could be ignored here before problem cleared).2 bits address.

/CS and /OE are GND.

PCLK= supplied by FPGA 48Mhz.

My side,only control /RD ,depend on FX3 /empty signal.

No matter controlled /RD signal,or simply treated /RD=!/EMPTY , all have problem as above red text.

One more clue,before I click steamer START,I select end point and it showed"BULK OUT,16384 bytes,15 maxburst"

Once problem occurred, the end point change back to default "IN...".

Any idea will be appreciated.

Thanks.

BR 

Steven

 

Steven Lin
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1 Solution
YatheeshD_36
Moderator
Moderator

Hello Steven,

997 Timeout error might be because the FX3 not having enough or no data to send to the host when it requests. 

Can you please let me know which base firmware you are using? and is it a Manual or Auto DMA channel between the GPIF and USB?

Please ensure that enough data is always committed and available on the USB side for the host to read in order to avoid 997 timeout error.

 

Thanks,

Yatheesh   

View solution in original post

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8 Replies
YatheeshD_36
Moderator
Moderator

Hello Steven,

997 Timeout error might be because the FX3 not having enough or no data to send to the host when it requests. 

Can you please let me know which base firmware you are using? and is it a Manual or Auto DMA channel between the GPIF and USB?

Please ensure that enough data is always committed and available on the USB side for the host to read in order to avoid 997 timeout error.

 

Thanks,

Yatheesh   

View solution in original post

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Stevenlm57
New Contributor

Dear Yatheesh,

Thanks  for your reply  

My transfer direction is from Pc =>usb cy3014=>Fpga. Slavefifo mode,stream out

So,the test data are generated from PC side  

Run my PC C++ exe, I received error code 997

If run Cypress Streamer , the result described in my previous red text

The firmware is from AN65974(sorry ,not sure,not in office now) and modify to fit my project.

It is auto DMA mode,burst mode.

I tried manual DMA  today ,still fail .

Please kindly help on this ,thanks

 

BR

Steven

 

 

Steven Lin
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YatheeshD_36
Moderator
Moderator

Hello Steven,

Since you are using the Slave FIFO mode, the master (FPGA) is responsible to assert the required control signals to get the output from the Slave device. 

If you have the UART line headers bought out from the board, please connect a USB-Serial bridge  to the UART lines and capture the debug logs. 

 Please let me know if a commit buffer failure is seen?

 

Thanks,

Yatheesh

 

 

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Stevenlm57
New Contributor

Dear Yatheesh,

Yes,there is a UART line in my board.

May I ask how to connect : 

directly connect CY3014 pin C2(UART-TX_spi_miso)  pin to USB-Serial bridge TXD pin ?

(I am using 32 bits)

BR 

Steven.

Steven Lin
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Stevenlm57
New Contributor

Dear Yatheesh,

OK,I successfully connect UART as I described before.

Please refer to attached below log file(I don't know how to upload file) and it stopped at error.

"

D_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNCYU3P_PIB_ERR_THR3_RD_UNDERRUNNo Error :18

Looks like all showed the same error : CYU3P_PIB_ERR_THR3_RD_UNDERRUN

And last message is No Error :18.

My fx3 firmware is based on AN65974 : 


/* 16/32 bit GPIF Configuration select */
/* Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT = 0 for 16 bit GPIF data bus.
* Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT = 1 for 32 bit GPIF data bus.
*/
#define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT (1)
/* set up DMA channel for loopback/short packet/ZLP transfers */
#define LOOPBACK_SHRT_ZLP

/* set up DMA channel for stream IN/OUT transfers */
#define STREAM_IN_OUT

/* set up MANUAL DMA channel for stream IN/OUT transfers */
#define MANUAL

#ifdef LOOPBACK_SHRT_ZLP
#define BURST_LEN 2 //1
#define DMA_BUF_SIZE (1)
#define CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U (2) /* Slave FIFO P_2_U channel buffer count - Used with AUTO DMA channel */
#define CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P (2) /* Slave FIFO U_2_P channel buffer count - Used with AUTO DMA channel */
#endif

#ifdef STREAM_IN_OUT
#define BURST_LEN 8 //16
#define DMA_BUF_SIZE (16)
/* Slave FIFO P_2_U channel buffer count */
#define CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U (2) //(8)
/* Slave FIFO U_2_P channel buffer count */
#define CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P (10) //(4)
#endif

#define CY_FX_SLFIFO_DMA_BUF_COUNT (2) /* Slave FIFO channel buffer count - This is used with MANUAL DMA channel */
#define CY_FX_SLFIFO_DMA_TX_SIZE (0) /* DMA transfer size is set to infinite */
#define CY_FX_SLFIFO_DMA_RX_SIZE (0) /* DMA transfer size is set to infinite */
#define CY_FX_SLFIFO_THREAD_STACK (0x0400) /* Slave FIFO application thread stack size */
#define CY_FX_SLFIFO_THREAD_PRIORITY (8) /* Slave FIFO application thread priority */

For your reference.

BR 

Steven.

Steven Lin
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Stevenlm57
New Contributor

Dear Yatheesh,

I am running system at Slave FIFO mode, my FPGA set :

/CS,/OE to GND.PCLK=48Mhz from FPGA.

A1,A0=VCC;/WR ,pkend=VCC.

And running at Synchronous SLAVEFIFO,  READ in burst mode.

FPGA only contrl /RD singal, /RD will always active after flagc =HIGH(not empty) ,and inactive immediately while flagc=low

For burst mode Read, keep /RD  low to read data until empty flag active.

All the data transfer from PC to my printer are all correct and good.

The only problem is PC stop at error code 997 sometimes.

And Streamer UART debug message  "CYU3P_PIB_ERR_THR3_RD_UNDERRUN" ?

Do I make something wrong ?

BR

Steven

 

Steven Lin
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Stevenlm57
New Contributor

Dear Yatheesh,

According to "CYU3P_PIB_ERR_THR3_RD_UNDERRUN" debug message,I think maybe  my problem is caused by  : my /RD signal did not de-assert 2 cycle latency before /EMPTY.

I will try to modify it.

 

BR

Steven.

Steven Lin
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Stevenlm57
New Contributor

Dear Yatheesh,

 thanks for your hint about UART. 

Good news. 
After modify RD signal control to fit spec,no more error now

BR

Steven

Steven Lin
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