CX3 suspend current

[Anonymous]

CX3 has a few low-power modes: suspend, standby, and core power-down.

   

If we want our device to go to a low-power state, but still be able to wake up on bus activity, suspend mode is the way to go (standby mode does not support wakeup from D+/D-/SSRX).

   

The suspend mode corresponds to the USB3.0 U3 link mode (link suspend). In the USB3.0 specification, paragraph 11.4.3, I read: "All USB devices may draw up to 2.5 mA during suspend." (This is also mentioned in table 11-2).

   

In the CX3 datasheet, DC specifications, page 18: suspend current for the USB block is 4.6mA. Roughly which portion of this current would go to U3TXVDDQ and U3RXVDDQ?

   

Is it possible to meet the 2.5mA specification with CX3 (suppose current consumption from other components is negligible)?

   

If not, could we do some standby-wake cycle to periodically check bus activity? In Table 5, there is no explicit mention of a timer as wakeup source for the standby mode. Would it be possible with the watchdog timer, without resetting the core and without too much overhead, so that we can just check the bus and go back to standby?

   

In short: is there a way to meet the 2.5mA suspend current specification in a CX3-based design?

       

Thanks,

   

Maarten

[Anonymous]

The guidelines to design a system with the lowest suspend mode current are listed below.

   

1. VUSB pin of CX3 to be connected to 3.3V instead of 5V (The firmware will need relevant modifications accordingly).
2. Provision to switch off all other elements in the system should be available. Only CX3 should be active/powered in the entire system. It should also be ensured that the standby current drawn by the other power regulators in the system should be negligible (when the regulators are disabled/shut off)
3. Very high efficiency switching regulators must be used to power the CX3 chip (1.2V, 1.8V and 3.3V). As per the above calculation the efficiency needs to be at least 85% at low currents. The below part numbers can be considered (owing to their high efficiency at low currents).
4. A low power 19.2 MHz clock oscillator chip must be used. The above estimate considers a current of 1 mA at 1.8V. 
5. It must be ensured in the system design that the standby currents of the turned off regulators are negligible and do not add up to a significant value (choose regulators suitably).
6. There must be provision in the design to disconnect the below circuits while entering suspend mode. The same has to resumed once out of suspend.  VDDIO2, VDDIO3,VDD_MIPI, REFCLK