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USB Superspeed Peripherals

GrAU_4638336
New Contributor II

Hello,

Through different questions already asked on your website, we have been able to solve majority of our issues. 
However, for the custom we are currently developing, we cannot have the USB3.0 interface working.
We would like to solve this issue in the next iteration of our custom board by understanding what is preventing us from using the USB3.0 interface on this very design. 

To avoid you some extra questions, I have resumed most of the things we developed, tested and probed.

  • Schematics / layout
    The board is using the example/guidelines given by cypress AN70707
    The board is using the reference given by eCon Systems for their CX3 + OV5640 Dev board schematics. 
    SSTX+ and SSTX- have both a 0.1uF 10% 6.3V capacitor placed close to the CX3.
    The connector used is a B8B-PHDSS(LF)(SN) with a custom cable using USB3.0 Type A on the other end.
    This cable is expected to work fine as it is used on another device.
    If necessary I can share the schematics/layouts related to the USB3.0 lanes. 

  • Firmware
    We did not apply any modification in the firmware regarding the USB3.0 interface and the clocks used. Ou custom board is working fine on USB2.0. Is there attention that should be given to something before expecting the CX3 to enumerate as USB3.0 ? At this stage, we are only looking to enumerate as 3.0, even with an example firmware and this is not working.

  • U3TX and U3RX powers
    We have originally measured a noise above 30 mV on these lanes and as such we have disconnected these lines from the onboard voltage regulator and supply them with a external stabilised power source which was giving 20 mV of noise. This didn't solve our problem and CX3 was still recognise as USB2.0 only.

  • SSTX and SSRX wires
    I have probed the SSTX and SSRX lanes before, during and after the firmware flash and can't see any real activity. The images attached are the results obtained in all of the case above. My oscilloscope is only rater for 110MHz, it might be complicated to probe these lanes correctly. 

  • Wireshark
    As I have seen in similar topics that Wiresharks data were important. I have attached to this message the Wireshark file recording from device being plugged in to firmware flashed and video correctly streaming. 

As a potential important point, the onboard clock is 19.2MHz and not 24MHz.

I'm absolutely available if you need any more info or if you want me to test something else.
Thanks i
My colleague @cam will also follow this topic and answer your potential questions. 

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17 Replies
Rashi_Vatsa
Moderator
Moderator

Hello,

Please refer to Q3 of this KBA  Trouble Shooting Guide for the FX3/FX3S/CX3 Enumer... - Cypress Developer Community  

Please check the point 1 (CX3 datasheet),2 (confirm noise level on AVDD, VDD, U3RXVVQ and U3TXVDDQ) and 4 of Hardware section and all points of firmware section.

Also, if possible please share the schematics of your custom board

Regards,
Rashi
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GrAU_4638336
New Contributor II

Hi Rashi,

Thanks for your feedback. We had already tested few of the points mentioned in your KBA. 

Here are the information I can give you.

  • 19MHz Clock signal is similar to Dev board clock signal, no apparent issue with it.

             GrAU_4638336_0-1626689913624.png

  • We are using a 110MHz oscilloscope to measure the noise on AVDD, VDD, U3RXVVQ and U3TXVDDQ. Is this type of oscilloscope enough for the measure of the noise?
    These are the results for AVDD, VDD, U3RXVVQ and U3TXVDDQ.
    GrAU_4638336_1-1626690090641.pngGrAU_4638336_2-1626690097322.pngGrAU_4638336_3-1626690106307.pngGrAU_4638336_4-1626690111413.png

     

  • We do not use a fully certified USB3.0 cable but we are confident that this cable is working as expected as it is used for another application. If you like, I can remove the connector we have and try to solder the wires directly to the board to avoid a potential failure from this connector. 

  • Here are the schematics  for the USB3.0 lines and power lines. Sadly, I cannot share the entire schematics on this page but I can provide them via email if needed.

    GrAU_4638336_5-1626690453632.png
    GrAU_4638336_6-1626690615367.png

     

    Thanks again for your help.

 

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Rashi_Vatsa
Moderator
Moderator

Hello,

19MHz Clock signal is similar to Dev board clock signal, no apparent issue with it.

>> Please confirm if this is the clock provided to CLK_IN pin of CX3. From your previous response "As a potential important point, the onboard clock is 19.2MHz and not 24MHz." , please let me know what is the 24 MHz clock? Is it the REFCLK?

Is this type of oscilloscope enough for the measure of the noise?

>> Ca you please let me know when is this traces captured? Please probe these pins when the device is plugged in to the USB 3.0 Host

 

Here are the schematics  for the USB3.0 lines and power lines. Sadly, I cannot share the entire schematics on this page but I can provide them via email if needed.

>> The schematics doesn't have the CX3 part of the design. Please confirm if the AC coupling caps are placed close to SSTX +/- pins of CX3.

Also, let me know if the device enumerates as USB 2.0 device when USB 3.0 connection fails

Regards,
Rashi
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GrAU_4638336
New Contributor II

Hi Rashi,

>> Please confirm if this is the clock provided to CLK_IN pin of CX3. From your previous response "As a potential important point, the onboard clock is 19.2MHz and not 24MHz." , please let me know what is the 24 MHz clock? Is it the REFCLK?

This is absolutely correct CLK_IN is provided with 19.2MHz. The 24MHz mentioned was only a comparison with a part of the Dev kit. 

>> Can you please let me know when is this traces captured? Please probe these pins when the device is plugged in to the USB 3.0 Host

I probed U3RX and TX on boot up and this is what I 
obtained for both of these.

Power is stable after 600us, is that fine? 

GrAU_4638336_1-1626816013548.jpeg

and with a tiny rush of 40mV at smaller scale. 

GrAU_4638336_0-1626816002531.jpeg

>> The schematics doesn't have the CX3 part of the design. Please confirm if the AC coupling caps are placed close to SSTX +/- pins of CX3.

I have shared the schematics with you via email. I can confirm that these AC coupling caps are less than 4 mm away from the pins. 



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Rashi_Vatsa
Moderator
Moderator

Hello,

Thank you for the details and schematics.

I will go through the schematics and let you know my comments.

Meanwhile please let me know if the device enumerates as USB 2.0 device when USB 3.0 connection fails. When in USB boot (PMODE[2:0] = Z11) does the device enumerate as Bootloader device?

Please let me know if Power-on-Reset RC components meet the minimum reset time (1ms). Also, the traces shared is for which power pin is it U3RXVDDQ/U3TXVDDQ/AVDD/CVDDQ

Regards,
Rashi
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GrAU_4638336
New Contributor II

Hi Rashi, 

Yes the device is correctly enumerating as USB2.0 and correctly working. We are able to get video stream from it.

Yes, the Power-on-Reset is set to 20 ms. 

The traces shared is for U3RXVDDQQ. 

Thanks again,

Greg

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Rashi_Vatsa
Moderator
Moderator

Hello Greg,

Thank you for the details.

As in your previous response, 40mV noise is seen on U3RXVDDQ which is more than 20mV. As per the KBA "Ensure that the noise on power supplies AVDD, U3TX_VDDQ, and U3RX_VDDQ is below 20 mV ". Please make sure that AVDD, U3TX_VDDQ, and U3RX_VDDQ have noise levels < 20mV.

Also, let me know if the problem is seen when device is connected to different USB host / PC. From the schematics the USB connector part is not clear. Please let me know more about it. 

Kindly, let me know if the PMODE lines are currently configured for USB boot or SPI boot

Regards,
Rashi
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cam
New Contributor II

Hi Rashi,

I believe we were measuring the noise incorrectly previously (we were using 10:1 attenuation on probe so was multiplying noise).

See attached noise on VDD, AVDD, TXVDDQ, and RXVDDQ lines. Noise was measured using AC coupling on the oscilloscope with a 20M bandwidth limit. 

I have also attached DC response on these lines when USB cable is plugged in 
  

AVDD-C40-DC-startup0.png

VDD_C43-DC-startup0.png

TXVDDQ-C36-DC-startup0.png

RXVDDQ-C22-DC-startup0.png

RXVDDQ-C22-AC.png

TXVDDQ-C36-AC.png

VDD-C43-AC.png

AVDD-C40-AC.png

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Rashi_Vatsa
Moderator
Moderator

Hello,

The USB 3.0 lines connection as shared by you over mail does not seem proper. We recommend to route the USB 3.0 lines directly to the USB connector. Please refer to AN70707 hardware guidelines and confirm if the USB 3.0 lines routing is as per the guidelines.

Regards,
Rashi
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cam
New Contributor II

Hi Rashi,

Can you please clarify what mean by route the USB 3.0 lines directly to the USB connector?
I believe we are currently doing that.

Thanks,
Cameron

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Rashi_Vatsa
Moderator
Moderator

Hello Cameron,

The USB lines (on the PCB) should be routed to the USB connector  directly i.e. not through wires. 

Regards,
Rashi
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GrAU_4638336
New Contributor II

Hello Rashi,

We do not enough space at the back of the camera and so we opted for a custom USB 3.0 connector/cable. The connector you are seeing is the other end of our USB3.0 cable.
We will try to implement an alternative board with USB type C connector.
Do you mind reviewing the schematics if we are sending that to you? 

Regards,

Greg

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Rashi_Vatsa
Moderator
Moderator

Hello Greg,

Sure, I can help you by reviewing the schematics.

As you are planning for Type C design, please refer to the following links  Designing FX3™/CX3-Based USB Type-C Products - KBA... - Cypress Developer Community

Solved: what is the recommendation design/connections for ... - Cypress Developer Community  

Regards,
Rashi
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GrAU_4638336
New Contributor II

Hello Rashi,

I don't think I understand your measure correctly. 
If you are referring to the initial spike, this is by equivalent what I obtained for the Dev Kit which is much higher than ours and yet working. 

GrAU_4638336_2-1626942638389.png
If then I take abstraction of this peak, everything seems under 20 mV. Is that correct ? 

Yes, this problem is occurring with different computers. 
Could you elaborate via email on what you would like to know about the connector part ?
I will send you some pictures. 

The PMODE lines are currently configured for USB boot.

Thanks for you help,

 

Greg

 

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Rashi_Vatsa
Moderator
Moderator

Hello Greg, 

Please find my comments below

- Please refer to section 4.2 of  AN70707, and let me know if the the 1.2-V power supply  does not drop below 0.83 V when an inrush event occurs.

- Kindly, probe and check if there is some communication seen on the USB Superspeed lines (SSRX/TX) when the device is connected

- Also, program USBBulkSrcSink firmware of the SDK on the CX3 and share the UART debug prints for us to check.

Regards,
Rashi
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cam
New Contributor II

Hi Rashi,

- Please refer to section 4.2 of  AN70707, and let me know if the the 1.2-V power supply  does not drop below 0.83 V when an inrush event occurs.

Please see previous response, confirming 1.2V line doesn't drop

- Kindly, probe and check if there is some communication seen on the USB Superspeed lines (SSRX/TX) when the device is connected

I have attached image of TX+ and TX- from the board. This stays consistent after startup.
There is no signal on the RX+ and RX- at any point

- Also, program USBBulkSrcSink firmware of the SDK on the CX3 and share the UART debug prints for us to check.

I have flashed that example, but the device hasn't appeared as a serial device. I will get @GrAU_4638336 to confirm on windows. 

 

Thanks,
Cam

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GrAU_4638336
New Contributor II

Hello Rashi, 

We do not have a UART outlet available on this board and as such cannot directly recognise this device as a serial communication device. Do you have this same example with a simulated CDC interface ? We use this simulated interface to debug our firmware on this board. 

Thanks,

Greg

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