CX3: Raised PCLK at GPIF II

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Anonymous
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Hello,

in the "HowToInterfaceMIPI.pdf" document you say that the maximum supported PCLK is 100 MHz.

We have a raw12 data format with 4 data lanes and maximum data rate of 400Mbit/s at each lane transferred using the CSI2 interface.

Is it possible to configure the MIPI CSI2 controller so that we can transmit our data in parallel over the GPIFII interface using a bus width of 24bit?

Thanks in advance!

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Keerthy_V
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In addition to GPIF II bus width change (to 24 bit), you have to change the data format in CyU3PMipicsiSetIntfParams() as CY_U3P_CSI_DF_RGB888 to transfer the video data through 24 bit parallel bus.

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Anonymous
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Yes, you can!

You need to set the macro GPIF_BUS_WIDTH to CY_U3P_MIPICSI_BUS_24 in cycx3_uvc.h file of your project.

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Anonymous
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Great. How will the data be aligned then?

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Keerthy_V
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2 pixel data will be sent in one clock cycle through the parallel GPIF II interface.

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Keerthy_V
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First like given 250 sign-ins 50 solutions authored

In addition to GPIF II bus width change (to 24 bit), you have to change the data format in CyU3PMipicsiSetIntfParams() as CY_U3P_CSI_DF_RGB888 to transfer the video data through 24 bit parallel bus.

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Anonymous
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Thank you for your support

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