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Hello,
We use a CX3, and we would like to know if the two delays of 10ms Max. indicated in figure 4 of its data sheet are correctly defined.
Could you please answer to the following questions?
- For the first delay, between the rising edges of VDD and VDDIO1, does the maximum delay really correspond to the time between the start of the two rising ramps?
- For the second delay, between the falling edges of VDDIO1 and VDD, does the maximum delay really correspond to the time between the start of the two falling ramps?
Otherwise, we are surprised that the rise/fall times are not taken into account. Indeed, different ramp rates of VDD and VDDIO1 power supplies may have the following consequence: VDDIO1 has not reached 0V before VDD power supply begins to decrease, as in the following figure:
Notes:
- The voltage ramp rate on core and I/O supplies is specified in the data sheet to be between 0.2V/m and 12V/ms.
- With these ramp rates (Min. and Max.), the time to reach a steady state can vary:
- From 100 µs (1.2V/0.012V/µs) to 6 ms (1.2V/0.2V/ms) for VDD,
- From 275 µs (3.3 V/0.012V/µs) to 16.5 ms (3.3V/0.2V/ms) for VDDIO1.
To have reference elements, we made the attached measurements with the Denebola RDK from e-con Systems:the power-off sequence confirms that VCCIO power supply may reach 0V after than VCC1P2 (VDD) has started to decrease. While the second measurement shows that the first delay is over 10ms.
However, are these timings acceptable?
Best Regards,
Eric.
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Hello Eric,
Power-up Sequencing:
Yes, you understood it right
Power-down sequencing
The VDDIO1 should have reached to 0 V before VDD starts decreasing. And the time difference berween these two events should be less than 10 ms. The ramp rate should be such that this condition is fulfilled.
The details (power-up/power-down sequence, ramp rates) mentioned in the CX3 data sheet is according to silicon requirements but so far we haven't seen failures of Denebola RDK.
Thank you for bringing this issue to our notice. We will check this with our design partner - econ systems
Regards,
Rashi
Rashi
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Hello Eric,
Power-up sequencing
1) For the first delay, between the rising edges of VDD and VDDIO1, does the maximum delay really correspond to the time between the start of the two rising ramps
>> The datasheet mentions "the maximum delay really correspond to the time between the start of the two rising ramps" assuming that both (VDD and VDDIO1) have same ramp rates.
As in your case (i.e the VDDIO1 and VDD ramp rates are not same), the maximum delay should be calculated between the end of the two rising ramps(For eg. when VDD and VDDIO1 reach the steady state 1.8V and 3.3V respectively).
Power-down sequencing
2) For the second delay, between the falling edges of VDDIO1 and VDD, does the maximum delay really correspond to the time between the start of the two falling ramps?
>> Yes, this condition is correct and should be met. This condition should override the ramp rate range mentioned in the CX3 datasheet i.e 0.2 - 12 V/ms. The ramp rate should be such that it fulfills this condition.
We will check with our design partner e-con systems regarding power down sequencing issue.
Regards,
Rashi
Rashi
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Hello Rashi,
Thank you for your prompt response, but I do not understand your conclusion.
Let me explain what I understood:
Power-up sequencing:
If I follow your rule (i.e. the maximum delay should be calculated between the end of the two rising ramps), I measure on Denebola RDK a delay of 180ms:
It seems that the issue is this timing. Do you agree with that?
Power-down sequencing
If the condition is correct and overrides the ramp rate range, only the delay between the start of the two power-down is important. No matter which power supply reaches 0V first, as in the following example:
I have additional questions for you: what is the risk? Is it the component's destruction due to a high leakage current?
Regards,
Eric
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Hello Eric,
Power-up Sequencing:
Yes, you understood it right
Power-down sequencing
The VDDIO1 should have reached to 0 V before VDD starts decreasing. And the time difference berween these two events should be less than 10 ms. The ramp rate should be such that this condition is fulfilled.
The details (power-up/power-down sequence, ramp rates) mentioned in the CX3 data sheet is according to silicon requirements but so far we haven't seen failures of Denebola RDK.
Thank you for bringing this issue to our notice. We will check this with our design partner - econ systems
Regards,
Rashi
Rashi
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Hello Rashi,
Thank you for your clarifications.
In summary of our discussion, here is the power supply sequencing that could be in the data sheet:
Is it right?
Regards,
Eric.
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Hello Eric,
Yes, this is right
Regards,
Rashi
Rashi