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USB Superspeed Peripherals

Anonymous
Not applicable

According to CX3 TRM page 8 the bus between MIPI CSI2 and GPIF II is 24 bit wide and has a max clock of 100 MHz. Therefore maximum transfer bandwidth is 2.4 Gbps. On the other hand, page 2 states supported MIPI CSI2 bandwidth of 1 Gbps X 4 lanes = 4 Gbps. The question is, when using 4 MIPI CSI2 lanes, how more than 600Mbps per lane are supported?

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Moderator
Moderator

The maximum bandwidth that CX3 can support is limited by the GPIF II block of CX3. As mentioned in TRM it can support till 2.4Gbps. So if you want to use all the 4 lanes, then CX3 can support only 600Mbps/lane. Else the video will not stream properly due to data loss.

On the other hand, if you are only using 2 lanes, then each lane can support up to 1Gbps.

The bandwidth is not limited by the MIPI receiver, but by the GPIF II block inside CX3.

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Moderator
Moderator

The maximum bandwidth that CX3 can support is limited by the GPIF II block of CX3. As mentioned in TRM it can support till 2.4Gbps. So if you want to use all the 4 lanes, then CX3 can support only 600Mbps/lane. Else the video will not stream properly due to data loss.

On the other hand, if you are only using 2 lanes, then each lane can support up to 1Gbps.

The bandwidth is not limited by the MIPI receiver, but by the GPIF II block inside CX3.

View solution in original post

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Anonymous
Not applicable

Thanks for the confirmation, Keaj.

Can you please escalate to the documentation team to correct the false claims of 4 Gbps?

For example, here is a erroneous quote from CX3 TRM page 2:

CX3 conforms to the MIPI CSI-2 specification (version 1.01) and supports up to four data lanes with speed

up to 1 gigabits per second (Gbps) per lane for a total bandwidth of 4 Gbps.

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Moderator
Moderator

Hi Ramzi,

The document is already updated.

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Anonymous
Not applicable

Hi,

I see conflicting informations here:

On the other hand, if you are only using 2 lanes, then each lane can support up to 1Gbps.

The bandwidth is not limited by the MIPI receiver, but by the GPIF II block inside CX3.

1. If the second quoted sentence is true in case of 2 lanes we should be able to use 2.4 Gbps / 2 = 1.2 Gbps per lane.

If not, it means the CSI2 D-PHY(=Mipi receiver) is actually introducing a limitation to 1 Gbps.

Is this correct ?

2. 2.4 Gbps bandwidth is only available when using RGB888 format. Otherwise GPIF parallel bus limits the total BW even more (Ex. RAW12 has 16 bits, max pxl clock=100 MHz --> max ideal BW is 1.6 Gbps (and actually less because 4 bits in the 16 bits bus are zero-padded, so real pixel information is only12 bits)

Can you please confirm my observations?

Nico

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Moderator
Moderator

Hello Nico,

Yes, the maximum bandwidth supported by the MIPI receiver is 1Gbps/lane.

But GPIF II block cannot support 4lane*1Gbps/lane bandwidth. It limits the total bandwidth supported by the chip to 2.4Gbps.

The bandwidth 2.4Gbps can be achieved when 24 bit parallel bus is used and the GPIF II interface clock is configured to 100MHz.

GPIF II bus width can be configured as 24 bit even if the input video format is not RGB888. In this case you need to select the output video format as RGB888 in the MIPI CSI configuration tool.

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