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USB Superspeed Peripherals

RiCh_4680461
New Contributor II

Hi Sir,

i am trying to bringup a sensor, which having following spec.

1. 720Mbps data rate per lane, 2 lanes.

2. mipi lane count: 2 lanes

3. sensor resolution: 1280x480

4. fps:  120fps

5. RAW12.

the sensor's clocking cannot be adjustable, i keep it as what it is. trying to configure CX3 parameters.

1. clock divider

2. fifo delay

3. multipiler

4. pixclk

after trial and error for a week, i figured it out, that PIXCLK has to be more than 108MHz in order to get correct image streaming.

2 questions:

1. Is 108MHz PIXCLK ok?  as spec said the max GPIF clock is up to 100MHz.

2.  i attached my cx3 configuration for your comment seeking for better settings possible reducing pixclk rate to be below 100MHz..configuration.png

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RiCh_4680461
New Contributor II

i managed to reduce the frame rate by half, now it looks OK now.

thanks

View solution in original post

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11 Replies
YashwantK_46
Moderator
Moderator

Hello,

Please try the following configuration as attached:

pastedImage_0.png

1.) Pixel Clock cannot be used above 100 MHz.

Please do the following and get back to me with the results.


Regards,

Yashwant

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RiCh_4680461
New Contributor II

HI sir,

please see my results. the pixclk rate still has to be larger than 107MHz in order to see image streaming correctly using AMCAP. also getting correct frm_sz..

pastedImage_0.png

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YashwantK_46
Moderator
Moderator

Hello,


Please confirm the resolution once.

Is it 1280 x 480 or 1280 x 483?


You should only specify the resolution that the sensor is configured for, in the CX3 Configuration Utility.

Can you please probe the PCLK with an oscilloscope and confirm the frequency that you see on the PCLK line?

Regards,

Yashwant

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RiCh_4680461
New Contributor II

1. 1280x483 is a correct resolution, the extra 3 rows in the bottom of image are embedded data.

2. PCLK freq measured, yes, it is same as what earlier table mentioned.

I was wondering that whether 720Mbps per lane ( 2 lanes) would be the bottleneck?

could you share what is the highest mipi data rate (2 lanes) that cx3 can process?

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YashwantK_46
Moderator
Moderator

Hello,

According to my response no.1:

I have provided a new configuration with pixel clock=96MHz where I have also added a fifo delay in the configuration.

And I can see in your response no.2, that the fifo delay isn't changed in the excel sheet that you provided and is still kept at 0.11uS

Please try the exact config that I provided with pixel clock=96MHz with the min fifo delay of 0.667 uS or more added as shown in the config that I provided.

Regarding response no.4:

The max supported MIPI data rate per lane is 1 Gbps and the total data rate is 2.4 Gbps

So, 720Mbps per lane won't be an issue or bottleneck.

Regards,
Yashwant

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RiCh_4680461
New Contributor II

Please try the exact config that I provided with pixel clock=96MHz with the min fifo delay of 0.667 uS or more added as shown in the config that I provided.

i tried the exact settings you recommended, but without any good luck.  i will find time test it again.

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RiCh_4680461
New Contributor II

below is the result of using recommended configuration. pixel clock=96MHz with the min fifo delay of 0.667 uS.

the issue there is the frm_sz inconsistent and not correct among frame.

right frame size should be 1236840 = 1280x483*2

pastedImage_0.png

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YashwantK_46
Moderator
Moderator

Hello,

Please do the following and let me know the results:

1.) In the CyU3PDeviceInit() API, set the setSysClk400 = CyTrue;    //this will enable a faster CPU

2.) Please increase the DMA buffer size

3.) Please add a fifo delay = 50 byte or more and try

Regards,
Yashwant

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RiCh_4680461
New Contributor II

i set setSysClk400 = CyTrue;   , also tried to modify DMA buffer size, but without good luck.

The buffer size i tried to modify is

#define CX3_UVC_DATA_BUF_SIZE                   (0x8FF0)

what is the max allowed size for CX3_UVC_DATA_BUF_SIZE?

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YashwantK_46
Moderator
Moderator

Hello,

You can use 48KB (0xC000) as the BUF_SIZE and the BUF_COUNT should be changed to 2.

Please try the following and update the values of the macros only.


Also, you can try with an increased FIFO delay value and PCLK=96MHz and share the UART debug logs.

Regards,
Yashwant

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RiCh_4680461
New Contributor II

i managed to reduce the frame rate by half, now it looks OK now.

thanks

View solution in original post

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