CX3 I2C master generates misleading pulse before stop condition

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MaOs_1615421
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Hi

I'm currently encountering a problem with the CX3 I2C master before the stop condition. It seems that after the last ACK the master waits too long to pull down the SDA line, allowing a pulse on the SDA line right after the slave releases it. I believe that causes some troubles in my slave's state machine as it assumes that another byte is going to be transferred. Indeed, the I2C communication is always stuck after the first write transfer. Is there a way to change the master's behaviour?

I'm using following code for testing:

uint8_t buf[2] = {0x01, 0x70};

preamble.buffer[0] = SENSOR_I2C_WRITE_ADDRESS; /* Slave address: write operation */

preamble.length = 1;

preamble.ctrlMask = 0x0000;

status = CyU3PI2cTransmitBytes (&preamble, &buf, 2,0);

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Hello Marc,

Thank you for the update about the problem on slave side.

Making the changes on the master side to get one more clock after the stop bit doesn't seem  feasible. I will still check it internally.

Please let me know why the device is behaving in such manner? Or why do you need one clock cycle more? so that we can find some other solution to it.

Regards,

Rashi

Regards,
Rashi

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