CX3 (CYUSB3065) PCLK_test, HSYNC_test and VSYNC_test outputs

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ChJo_4599956
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This is my first post in the forum, so please bear with me. I am working on a project which uses a CYUSB3065 CX3 chip to get images from a MIPI interface to USB Superspeed, and am having problems getting it working reliably. It will sometimes work intermittently, and when it does, the results are fine, but frequently it will just refuse to receive MIPI data.

The first thing that puzzles me are the PCLK_test, HSYNC_test and VSYNC_test outputs from the chip. Where is the documentation that describes how they are generated? When MIPI data is being received, I get sensible signals on HSYNC_test and VSYNC_test pins. When the MIPI data is not being received successfully, I get nothing on those pins.

However, PCLK_test is more confusing. What governs the frequency I should be seeing on there? According to the configuration tool in EZ-USB the pixel clock should be 96MHz (which is correct for my camera). However, I actually measure 76.8MHz on PCLK_test.

This is suspicious because I'm using an external REFCLK of 24MHz rather than the internal 19.2MHz one. However, if the chip had somehow decided to use its 19.2MHz reference clock, the pixel clock would be wrong in exactly that way. I've checked and my 24MHz clock is present and working.

Is there something I've missed? What determines the frequency of PCLK_test?

Thank you

Chris

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ChJo_4599956
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5 replies posted First solution authored First reply posted

I think I've now solved the problem. The PCLK frequency I'd set was too high. I naively set it to the same as the pixel clock in the cameras, but it seems that's wrong and I should reduce it, presumably because wherever is handling the data at that point doesn't have a horizontal blanking interval. I reduced it from 96MHz to 82MHz and now I have reliable data transfer.

Interestingly the symptoms of it being too high were that it would work for a few minutes in the morning, then get less and less reliable until there were just occasional pulses on HSYNC_test and never a complete frame.

I also note that HSYNC_test outputs one pulse for each line of video, not including any vertical blanking interval. The pulses are evenly spaced through the frame. So my 480-line video at 100Hz frame rate gives exactly 48kHz on HSYNC_test. This again is significantly different from the horizontal frequency on the camera.

I hope these notes help someone else.

Chris

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3 Replies
ChJo_4599956
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5 replies posted First solution authored First reply posted

Correction: I'd misunderstood the board I have here (I have inherited the design from someone else). The REFCLK is actually 19.2MHz, and the 24MHz source isn't used. So I've corrected the CX3 PLL settings accordingly and now have 96MHz at PCLK_test, but still no HSYNC_test or VSYNC_test.

 

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Hemanth
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First like given First question asked 750 replies posted

Hi,

Can you please post the screenshot of 'CX3 receiver configuration' tab of utility.

Issue can also be due to incorrect MIPI data. Please verify that as well.

Regards,

Hemanth
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ChJo_4599956
Level 1
Level 1
5 replies posted First solution authored First reply posted

I think I've now solved the problem. The PCLK frequency I'd set was too high. I naively set it to the same as the pixel clock in the cameras, but it seems that's wrong and I should reduce it, presumably because wherever is handling the data at that point doesn't have a horizontal blanking interval. I reduced it from 96MHz to 82MHz and now I have reliable data transfer.

Interestingly the symptoms of it being too high were that it would work for a few minutes in the morning, then get less and less reliable until there were just occasional pulses on HSYNC_test and never a complete frame.

I also note that HSYNC_test outputs one pulse for each line of video, not including any vertical blanking interval. The pulses are evenly spaced through the frame. So my 480-line video at 100Hz frame rate gives exactly 48kHz on HSYNC_test. This again is significantly different from the horizontal frequency on the camera.

I hope these notes help someone else.

Chris

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