Continuing from this question since it was closed before I could post a follow-up...
Here are the 1080p@60 2 lane MIPI configuration we're using. Not able to get a stable HSYNC or VSYNC from the CX3 debug pins. Please advise how we should update the settings:
CX3 supports a maximum of 1Gbps per lane if you use upto 2 lanes. The CSI clock setting in the MIPI configuration utility is DDR and hence if you configure it as 720, then it means 1440Mbps per lane. This is not supported by CX3. If the requirement is 720Mbps per lane, then please configure the CSI clock setting as 360. The remaining settings seems to be fine.
Please make the above modification and check if you are able to see stable HSYNC and VSYNC by probing the HSYNC and VSYNC test points on CX3. If it is not stable, please share the captured traces of HSYNC and VSYNC so that we can understand the problem better.
Tried it without success.
When I change the CSI clock setting to 360M or any other value I don't see a change in the calculated MIPI settings; same for THS-Zero and THS-Prepare. Shouldn't the contents of cyu3mipicis.c that is generated by the tool change if those settings are changed?!
When I enable 2 lanes I see the message: "ERROR: Parallel output cannot finish within 1 line. User faster Output Pixel clock and/or wide H-Blanking". But output clock cannot exceed 100MHz and for 1080p60 we need ~124M.
By changing CSI clock setting, the contents of cyu3mipicsi.c may not be changed. This will change when you make any changes to the MIPI Receiver configuration settings. By my previous comment on this thread, I wanted to ensure that the data rate per lane is 720Mbps only and not 1440Mbps. I also wanted to make you aware that CSI clock can be set to a maximum value of 500MHz only.
From the snapshot of MIPI configuration structure that you shared in the previous response, I see that the number of lanes is 2. Please share the snapshot of the MIPI configuration utility when for the following statement in your previous response:
"When I enable 2 lanes I see the message: "ERROR: Parallel output cannot finish within 1 line. User faster Output Pixel clock and/or wide H-Blanking". But output clock cannot exceed 100MHz and for 1080p60 we need ~124M."
I will verify the settings at my end and let you know my comments on the same.
Also, I understand that when you changed the CSI clock to 360MHz and tried to stream, the result was still failure. Please share the captured traces of HSYNC and VSYNC from the CX3 test points for us to debug the issue.
I made the changes as you specified. We're in the process of spinning a new board to eliminate SI as a source of the problem. If the problme persists I will capture HSYNC/VSYNC for you. Currently they're not stable meaning HSYNC duration and width changes rapidly as does VSYNC>
Thank you for the update. We understand that you are developing a new board to eliminate SI problems. Meanwhile, can you share the snapshot of the MIPI configuration utility as requested in my previous response? Also, please let us know if you are packing/padding the incoming data.