CX3 1080p@60

[ArFa_1311016]

Hello,

I am trying to get OV2740 at 1080p@60Hz RAW8 working with CX3. Streaming with 1080p@30Hz works just fine. The sensor MIPI output is fixed @ 720 Mbps / lane, for either mode.

My PCLK is 78MHz for 1080p@30. FIFO delay is set to 1. Everything works.

For 1080p@60 I change the lane count on structure that is passed to CyU3PMipicsiSetIntfParams to 2. GPIF is set to 16-bits wide. I don't think there is a need to change any other settings. Probing VSYNC, HSYNC output of CX3 I can see a good and stable VSYNC that looks correct. HSYNC however varies in length, although the overall size of HSYNC active region looks OK when zoomed out. Meaning the total frame active time is OK. I have tried other FIFO delay settings, but that's not fixing anything.

Do you have any suggestions? PCLK should be ~124MHz but it can't exceed 100MHz so I'm assuming the data is just pushed through the wide 16-bit GPIF. Is this correct?

[JayakrishnaT_76]

Hello,

Please share the following details so that I can understand the problem better:

1. Snapshots of the CX3 Receiver Configuration Settings in the MIPI configuration utility.

2. UART debug logs.

In addition to this, please let me know if you are packing or padding the incoming data into 16 bits.

Best Regards,

Jayakrishna

[ArFa_1311016]

Hello Jayakrishna,

CX3 Receiver settings for 1080p60 are as follows:

CyU3PMipicsiCfg_t OV2740_RAW8_1080p60 =

  {

    CY_U3P_CSI_DF_RAW8,                 /* CyU3PMipicsiDataFormat_t dataFormat */

    2,                                  /* uint8_t numDataLanes */

    1,                                  /* uint8_t pllPrd */

    51,                                 /* uint16_t pllFbd */

    CY_U3P_CSI_PLL_FRS_500_1000M,       /* CyU3PMipicsiPllClkFrs_t pllFrs */

    CY_U3P_CSI_PLL_CLK_DIV_8,           /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

    CY_U3P_CSI_PLL_CLK_DIV_8,           /* CyU3PMipicsiPllClkDiv_t parClkDiv */

    0x0506,                             /* uint16_t mClkCtl */

    CY_U3P_CSI_PLL_CLK_DIV_8,           /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

    1920,                               /* uint16_t hResolution */

    100                                 /* uint16_t fifoDelay */

  };

REFClock is 24MHz

MCKLK is 6MHz

We're using our own CX3 UVC firwmare, which has been production proven and works fine for 1080p30. In any event our issue is before sending data out of USB. We're seeing irregular HSYNC lines out of the MIPI receiver. The GPIF bus is set to 16 bits, with other modes (including 1080p@30) this gives us Y1,00,Y2,00, with 0's being the UV samples. We output the video as YUV2 and it displays just fine on the host side for other modes. We're only having this problem with 1080p@60 which is the only 2-lane mode we are using.

My question is:

1. How does pixel packing work for 1080p@60 @ 16-bits? Will we get Y1,Y2? If not how does CX3 push the data through w/ a 78MHz pclk?
2. How can we debug the HSYNC issue?

[JayakrishnaT_76 · Accepted solution]

Hello,

Please find my response for your questions below:

1. When the incoming data is packed, the GPIF samples the data as Y1,Y2. To reconstruct the original image, you need to develop your own host application.

2. Generally, the HSYNC and VSYNC becomes unstable when the MIPI configuration settings do not match with the sensor settings.

According to my understanding, you are using the MIPI configuration settings for 1080p30 by changing the no of lanes from 1 to 2 for 1080p60. Please correct me if Iam wrong. If Iam correct, then this is not proper. You need to create another MIPI configuration for the 1080p60. If you have already created it, then please share the snapshot of your settings as that shown below:

Best Regards,

Jayakrishna