Hi, I'am new to the CX3 environment and started to build a application for converting 1928*1088 @ 60FPS RAW10 MIPI to USB 3.0 UVC , we are using the CX3-RDK board from E-CON systems and we are designing our own daughter board. When using the configuration tool iam getting certain errors so need a bit of clarification on it. (Attached screenshots for your reference). In Image sensor configuration the CSI Clock is it referring the MIPI PIXEL Clock coming from the sensor? in that case our sensor gives 90Mhz but providing that value the tool is expecting a minimum value around 316Mhz. Our sensor has speed of 720Mbps per lane and we are using 2 lanes so i guess the output video format can be 16bit output
After giving these settings in image sensor configuration going on to CX3 receiver configuration following errors were occurred
Also tried to change the CSI Clock to the minimum expected value and changed output configuration to 24bit which eliminated the Parallel output error (Explanation on this problem would be great), but still cant achieve output pixel clock properly.
Is my configuration is proper? if not what iam missing?
You can use attached configuration. Parallel output is 24 bit.
Make sure to configure the MIPI Transmitter to the CSI clock chosen in the configuration.
Also note that the Hresolution data in bytes needs to be a muliple of 4 bytes. Hence I have changed it to 1920.
You can ignore the error shown at CSI clock in the attached configuration.
We will apply this setting and try it out.
"Make sure to configure the MIPI Transmitter to the CSI clock chosen in the configuration."
Is that means the Sensor MIPI Clock (ie Pixel clock )should be configured to 350Mhz?
350MHz MIPI clock from the transmitter to CX3 mipi interface is needed to meet the requirements of above configuration. So it is good to check the same with the sensor vendor.
In the first post it is mentioned that "Our sensor has speed of 720Mbps per lane". If 90MHz MIPI clock is fixed, then how is it possible to achieve 720Mbps per lane? Can you please clarify this?
If MIPI clock cannot be changed to more than 90MHz, then with the same resolution and data format, 15FPS can be achieved.
Its found the pixel clock is 90Mhz and PHY-Serial clock is 720Mhz, so we applied the same setting in the configuration as shown in the below image
we are still facing error in the clock which says 752.03 is the minimum value and in the output pixel clock which says 12.6.3 is the minimum.
Next we change the i2c read and write address as well as the initial i2c configuration table in cyu3imagesnesor.c file
we are not using any master clock from CX3 , instead we are using external crystal for sensors master clock.
Anything else we need to change? because if we build the following error occurs
Note: we are also not using any GPIO to control the sensor
Description Resource Path Location Type
THS Zero is less than Min Value 752.03 for OH2M_RAW10_FHD cx3config.cycx /OVOH02A10_CX3 Unknown Problem
Output Pixel Clock is less than Min Value126.31680297851562 for OH2M_RAW10_FHD cx3config.cycx /OVOH02A10_CX3 Unknown Problem
350MHz CSI clock is enough for the above configuration. Is it possible to configure to 350MHz instead of 720MHz?
If it is not possible, you can try testing by ignoring above shown errors (CSI clock min value 752 MHz, Pixel clock 126 MHz)