cancel
Showing results for 
Search instead for 
Did you mean: 

USB Superspeed Peripherals

Milka
New Contributor II

Hi Rashi!

I closed the previous forum thread by mistake, sorry 🙂 Previous thread: https://community.cypress.com/t5/USB-Superspeed-Peripherals/Broken-Data-correct-streaming-FX3-data-t...

I attach my ILA screenshots of DMA flags and current structure of slave fifo model + fpga files. 

Thank you!

0 Likes
1 Solution
Milka
New Contributor II

Hi Rashi!

I had to replace my no name chinese cable with a better one and it worked! Thank you for your help 😃 Well, in the future I will always be more attentive to little things!

Don't buy cheap & no name chinese cable!

Thank you!!!

View solution in original post

0 Likes
21 Replies
Rashi_Vatsa
Moderator
Moderator

Hello,

Thank you for the details.

As asked in the previous thread, please confirm that the data sent from the FPGA is a incrementing data  like 1,2,3... as shown in FIFO generator in the document.

If yes, please send 16 KB of data or data equal to the size of DMA buffer  from FPGA and read the data on USB Control Center. Please share the snippet of the data read at the control center.

If the data sent is received properly, repeat the test until the problem is seen. Share the snippet of Control center when the issue is seen

This test is to understand the problem better.

Regards,
Rashi
0 Likes
Milka
New Contributor II

Hi Rashi!

I attach my answers.

Thank you!

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

As per the problem seen in PART 1 of the attached document, I could see 0x0A every time after the point where you have indicated.

The fifo_tx_prog_full bit is seen as 1. I understand that fifo_tx_prog_full is a flag showing the status of FIFO generator internal to FPGA. Is my understanding correct?

If yes, it seems that flag is set from FPGA side. Please check the slave FIFO interfacing signals at that instance to check if fifo_tx_prog_full is set by the FPGA. 

Please confirm if the GPIF state machine is the default one as in AN65974. Also, if possible please share the firmware for us to check the DMA channel configuration.

For problem mentioned in PART2, please confirm if the problem is seen at only one instance when the data is read over USB. If yes, is this the same place at which the problem is seen always or does it vary? 

Please let me know which host application is used to read the data mentioned in PART2 of the document

Regards,
Rashi
Milka
New Contributor II

Hello,

1. As per the problem seen in PART 1 of the attached document, I could see 0x0A every time after the point where you have indicated. 

Yes, afeter 3 click this flag is set to 1 - FPGA

2. The fifo_tx_prog_full bit is seen as 1. I understand that fifo_tx_prog_full is a flag showing the status of FIFO generator internal to FPGA. Is my understanding correct?

Yes - this flag of Xilinx Generator 13.1 (programmable overflow buffer)

it simply indicates an internal overflow of the FPGA FIFO generator, which in turn may mean that the FX3 does not have time to pick up from FPGA FIFO

3. About Method 2:

If yes, is this the same place at which the problem is seen always or does it vary?

Yes, the problem changes, but not significantly

The number of incorrect 16-bit words is from 9-50 words per 100 MB
They appear at the very beginning if i request 100 Mb

If I request 200 MB of data Then They appear after (~ 100-127 MB
This does not seem to be some kind of exact repeatability, but around these areas(0-10mb and 100-130mb) they appear.

5. Please let me know which host application is used to read the data mentioned in PART2 of the document

My application using CyAPI C++ application library VERSION 1,2,1,0

I attached my current fx3 firmware based on  AN65974 to message

========================================================
If I can't solve the problem with the firmware above. I will be using fresh AN65974


Now I'm trying to recreate the firmware based on AN65974
I attach first results with Example from AN65974.

 

0 Likes
Milka
New Contributor II

Hi Rashi!

I put new information about example of AN67954 & My - FPGA Stream IN State Machine diferencies.

Thank you for answers!

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

Thank you for the details.

From the state machine description, I understand that once the Flag B (watermark) is low(0) the nest state will be Write One Word if Flag A is high (1). 

Please let me know many bytes /data words are written when in Write One Word state.

From the firmware the watermark value is 8 which means that after the clock edge at which Flag B is sampled LOW(0), 4 data words (in this case - 4 * 32 bits/4 bytes) should be written to FX3.

From AN65974 "The number of data words that may be written after the clock edge at which the partial flag is sampled low = watermark x (32/bus width) – 4"

Instead of monitoring Flag A in Write Delay state and then transitioning to WRITE ONE WORD, you can directly count 4 data words after Flag B (watermark) is sampled low(0) i.e.  SLWR = 0 for 4 clock cycles after Flag B is sampled low (0) .

It is recommended that Flag B (watermark) is monitored to stop the data transfer from FPGA and Flag A (DMA ready) is monitored to start the data transfer to FX3.

Please try modifying the state machine as explained above and let me know if that works

Also, check if the FPGA FIFO generator flags are also configured in sync with the DMA flags as state transitions in your state machine are dependent on FPGA FIFO flags too.

Regards,
Rashi
Milka
New Contributor II

Hi Rashi!
I tried to draw and do as you said. Works but with its own errors. May be not correctly realisation. But the speed of work is already higher than 300 Mb / s, this is very pleasing! 😃

My First results: https://www.evernote.com/shard/s498/sh/793fe540-a339-1a13-d9bf-5fc585480d9d/7387aabc8853ca5e1ab89c76...

In the last example, the speed hangs about 305 mb / s:

https://www.evernote.com/shard/s498/sh/5dce6782-97b8-7c1d-9a7f-499b3e8b09fc/16b8a4b89025c14e03233f82... 

 

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

From this link 

Under "If not using programms(FX3 Clients, Streamer C++ ... etc) we see:" the second waveform shows that data is being written (SLWR is low) even when FLAG A and FLAG B are LOW (i.e. DMA Buffer of FX3 is FULL)

Please let me know when is this trace captured.

In the second trace under section " If i run C++ Streamer after analyse fpga signals" , burst writes are not done as SLWR is toggled while switching between stream_in_write and stream_in_write_wr_delay.

Please let me know why do you use stream_in_write_wr_delay with SLWR =1. What is the purpose for stream_in_write_wr_delay. 

As per AN65974, in the  write delay state the SLWR =0 (the data writing is on) and the last few words are written to FX3 as per the watermark value. In your case, 4 words needs to be written (i.e. SLWR needs to be LOW for 4 clock cycles) after FLAGB is sampled low.

Watermark flag is used so that the FPGA/master can monitor the flag and stop the high speed transfers (SLWR =1) accordingly. 

Please let me know the FIFO size of FPGA. It would be easier if the FIFO size of FPGA is equal to DMA buffer size of FX3 (16 KB). From the traces I could see that TX_FIFO_EMPTY flag toggles multiple times while a single 16 KB transfer is taking place.

Regards,
Rashi
Milka
New Contributor II

Hi Rashi!
Thank you for replies!

My updated implementation: link 

I not tested this implementation in my program, because my target is 300 mb / s. I see now no problem when i get 16kb bulk transfers in USB Control Center but speed is low.  I can't run my program.

In tests always i using 75 Mhz frequency to generate FIFO data.

I tried run old implementation and see speed is 295 mb / s at 75 Mhz and 398 at 100 Mhz. This means the troughtput and firmware of FX3 is ok and problem in implementation in fpga. (Now it seems to me that this is incorrect handling of FIFO and DMA signals).

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

Glad to hear that the data was received as expected after changing the FPGA implementation.

As the data received is proper, the FPGA implementation seems fine now.

In tests always i using 75 Mhz frequency to generate FIFO data.

>> Please let me know if tests are done with 100 MHz clock with the new implementation. If yes, please let me know the data rate seen on the streamer app. Please try this configuration PPX = 32  and Xfers to Queue = 64

To improve the data rate, we can try the following:

- Increase DMA buffer size to 32 KB and reduce the DMA buffer count (CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U to 4 and CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P to 2 )) and also the FPGA FIFO size to 32KB

Please let me know if there is some improvement with this.

Regards,
Rashi
Milka
New Contributor II

Hi Rashi!

My tests: link

Update(60 Mhz Test):  

I set 60 Mhz and  the maximum speed (C++ Streamer) was reached 186 mb at
PPX = 1 XTQ = 64 ,
but if PPX=2, XTQ = 8 speed is rising to 180 mb and than is drop, Failure counter is increasing

 

 

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

I understand that the DMA and FIFO configuration for test 2 is 32KB. Is that right?

If yes, please try 16 KB DMA buffer size and FPGA FIFO at 100 MHz. Also, confirm if the system clock is 403.2 MHz

clkCfg.setSysClk400 = CyTrue;

Please try this configuration PPX = 32  and Xfers to Queue = 64 for the above test. If failures are seen, try increasing the timeout period and let me know the results

But in USB Control Center i see next information:

>> I didn't understand the errors that you are seeing. Please elaborate.

Regards,
Rashi
Milka
New Contributor II

Hi Rashi!

My latest tests and replies : link 

 

0 Likes
Milka
New Contributor II

Hi Rashi!

My new results and replies: link

I update pictures about latencies in my notes.

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

Can a state machine in different Implementations work well with only 16KB(configurable burst lenght) of data? And when transmitting to PC in a stream, have errors (if used wrong implementation)?

>>  The AN65974 FPGA implementation is not dependent on DMA buffer size of FX3. 

From the difference, I noticed that Flag B (watermark) is checked before starting the data transfers. Please let me know why do you check for FLAG B = 1 ( in comparison 6). The control will go to stream_in_write only when Flag B  = 1.

I wanted you to check the following setting

 SETTINGS:
DMA=16 KB,
FPGA FIFO = 100MHZ,
PCLK (clock from FPGA to FX3) = 100MHZ,
BUF_COUNT_P_to_U (8)
BUF_COUNT _U_to_P (2)
FPGA SIZE = 16 KB
WATERMARK = 8,
clkCfgSysClk400 = True
You can vary PPX, Xfers per Queue and timeout period such that no failures are seen and the data rate increases.
In the errors that are seen, I understand that FPGA FIFO sees overflow. Is my understanding correct? If yes, this could be possible when the USB host is not consuming the data as fat as it is written to FPGA FIFO. DMA Buffer will not be available (FLAG A - LOW) if USB host doesn't consume the DMA buffers. 
 
To avoid FPGA FIFO overflow, we need to consume the data in DMA buffers as fast as possible. This can be done by using streamer app.
 
The data rate can be increased in two ways
- Tune  PPX, Xfers per Queue and timeout period such that no failures are seen and the data rate increases.
- Increase the DMA Buffer size (reduce the DMA buffer count) and increase the FPGA FIFO size. Please note that the implementation would be easier if DMA buffer size and FPGA FIFO are kept of same size.
Regards,
Rashi
Milka
New Contributor II

Hi Rashi!

My new implementation and replies: link

Updated

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

From the description in the link, I understand that the only problem seen is that the FPGA FIFO overflows. After the changes in the watermark flag the  bandwidth requirement is also met. 

Please confirm if the data sent from the FPGA is correctly received by FX3. If yes, you would need to check the FPGA implementation for the synchronization of the FPGA FIFO flags and DMA flags. From the results you shared it seems that the SlaveFIFO interface of FX3 is working as expected. Is that correct?

Regards,
Rashi
Milka
New Contributor II

Hi Rashi!

Sorry for the long answer

I have moved away from tests and

I backed to old realistation and add flag to block write in fifo by (fifo_prog_full).

This flag is (Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the assert threshold. It is deasserted when the number of words in the FIFO is less than the negate threshold.)

In my last test i get 0 errors after download binary file. But speed is lowed to 270 mb/s on 75Mhz.

Does this mean that USB is not capable of instantly correctly delivering a volume of information equal to 300 mb / s at 75 MHz (75 * 32/8) = 300 Mb / s.

Could this be due to PC USB controller delays?

Now i try find different variations of ppx,timeout,xfers to queue for fast transferring 300mb/s but not yet sucessful.

I'm looking for solutions to the problem.

Thank you!

 

 

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

Does this mean that USB is not capable of instantly correctly delivering a volume of information equal to 300 mb / s at 75 MHz (75 * 32/8) = 300 Mb / s.

>> Please let me know if you have tested this using DMA Manual channel or AUTO Channel. DMA AUTO channel can be used to increase the  data rate.

The SlaveFIFO interface has other interfacing signals which are related to sampling of the data. So, due to that the data rate can be low than expected. Also, check this app note which mentions parameters responsible for USB 3.0 speed of FX3 https://www.cypress.com/documentation/application-notes/an86947-optimizing-usb-30-throughput-ez-usb-...

Now i try find different variations of ppx,timeout,xfers to queue for fast transferring 300mb/s but not yet successful.

>> Please try changing the DMA channel to AUTO mode by disabling the macro #define MANUAL in the firmware.

Regards,
Rashi
Milka
New Contributor II

Hi Rashi!

I had to replace my no name chinese cable with a better one and it worked! Thank you for your help 😃 Well, in the future I will always be more attentive to little things!

Don't buy cheap & no name chinese cable!

Thank you!!!

View solution in original post

0 Likes
Rashi_Vatsa
Moderator
Moderator

Hello,

We are glad to hear that the problem is resolved now!

Regards,
Rashi
0 Likes