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USB Superspeed Peripherals

WGT_4383351
New Contributor II

In AN87216, is Fig.5 and Fig.6 for generic example for read/write of slave, or the exact timing in the Master/Slave setup?

In the master state machine, WR and CS are asserted at the same state, this is different than Fig.6, in which WR is asserted 1 clock later after CS.

In the master state machine, in the state WR_FLAG, why is CS delayed and WR early? Will this make WR asserted before CS?

And I'm not sure why there is choice of early(2 cycle) and delayed(3cycle) here, does this mean there is pipeline between the state machine output and the IO pad? For 100Mhz pipeline should not be needed.

I need to add another two state machine chains to implement 2 RX and 2TX thread, can't proceed until it is clear how to set early and delayed.

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1 Solution
YashwantK_46
Moderator
Moderator

Hello,

1.) In the master state machine, the SLCS is asserted later than SLWR but please take a look at the slave machine, where the slave waits for both the SLCS and SLWR are asserted to reach the WRITE state in the state machine.

The master state machine available with the appnote AN87216 is provided as an emulation to a FPGA using another FX3 as master and a FPGA master would only need to

But, due to the limitation of GPIF designer, there can be only 8 early signals.

The same information has been conveyed in the gpif2_designer_userguide.pdf that has referred in the interaction no. 1 on Page no. 56.

pastedImage_0.png

2.) They can be asserted at the same time, but since there is a limitation on the early signals to only 8 output signals, you will have to take care of the assertion of the signals correctly according to the slave state machine.

3.) The concept of early and delayed signal exists in the GPIF designer can be understood from the following thread: Re: AN82716: SLWR and SLCS

Regards,

Yashwant

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10 Replies
YashwantK_46
Moderator
Moderator

Hello,

In the master state machine, in the state WR_FLAG, why is CS delayed and WR early? Will this make WR asserted before CS?

--> Yes, since the CS is delayed, it will be asserted a clock cycle later than the WR even when they are asserted in the same state in the state machine.

As shown in the gpif2_designer_userguide.pdf, the DR_GPIO action does the following:

pastedImage_2.png

The following file can be found in the SDK path: C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\GPIFII_Designer\gpif2_designer_userguide.pdf

Please follow the section 4.3.6 Action - DR_GPIO on Page No. 35 of the same document as above.

Regards,
Yashwant

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WGT_4383351
New Contributor II

1. Why is CS asserted later than WR? In Fig. 6 in AN, CS is asserted first.

2. Can they be asserted at the same time - both early or both delayed?

3. When will DR_DATA be asserted in sync mode? 2 clock or 3 clock later after the state that has that action ? These concepts are all inter-confusing.

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YashwantK_46
Moderator
Moderator

Hello,

1.) In the master state machine, the SLCS is asserted later than SLWR but please take a look at the slave machine, where the slave waits for both the SLCS and SLWR are asserted to reach the WRITE state in the state machine.

The master state machine available with the appnote AN87216 is provided as an emulation to a FPGA using another FX3 as master and a FPGA master would only need to

But, due to the limitation of GPIF designer, there can be only 8 early signals.

The same information has been conveyed in the gpif2_designer_userguide.pdf that has referred in the interaction no. 1 on Page no. 56.

pastedImage_0.png

2.) They can be asserted at the same time, but since there is a limitation on the early signals to only 8 output signals, you will have to take care of the assertion of the signals correctly according to the slave state machine.

3.) The concept of early and delayed signal exists in the GPIF designer can be understood from the following thread: Re: AN82716: SLWR and SLCS

Regards,

Yashwant

View solution in original post

WGT_4383351
New Contributor II

In AN87216, is Fig.5 and Fig.6 for generic example for read/write of slave, or the exact timing in the Master/Slave setup?

If it is not the exact  timing for the Master/Slave setup, the what is the timing requirements of GPIF master and slave interfaces?

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YashwantK_46
Moderator
Moderator

Hello,

The FPGA should follow the timing diagram from the application note as it explains the timing according to which the slave functions ( read/write ) depend upon and should be taken care by the master.

Regards,

Yashwant

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WGT_4383351
New Contributor II

There is no FPGA, this is the master/slave setup, both are FX3.

In Fig.6, CS is asserted before WR, but in the master GPIF project, CS is asserted later than WR, why?

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WGT_4383351
New Contributor II

"

They can be asserted at the same time, but since there is a limitation on the early signals to only 8 output signals, you will have to take care of the assertion of the signals correctly according to the slave state machine

"

Why since this then will that? Is there a causality here?

Why isn't all GPIOs set to be delayed to be simpler?

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WGT_4383351
New Contributor II

Did you mean "since there is a limitation on the early signals to only 8 output signals, you have to set both CS and WR to be delayed, and as a result you may need to check whether this works with the slave state machine"?

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YashwantK_46
Moderator
Moderator

Hello,


That's correct.


You can try assigning both the signals as CS and WR as early or delayed but you may need to check whether this works correctly with the slave state machine.

Regards,

Yashwant

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WGT_4383351
New Contributor II

Please check this thread Complex GPIF configuration , follow on discussion is needed.

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