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I've been trying to use AN65974, Designing with the EZ-USB® FX3™ Slave FIFO Interface, as an example for my own design. I've modified the stream out VHDL code for my purposes, but I'm having trouble with the stream in. In the slaveFIFO2b_streamIN module, even if I simply change the line that sets the data from
data_gen_stream_in <= data_gen_stream_in + '1';
data_gen_stream_in <= data_gen_stream_in + "10";
or even just make it a constant and leave everything else the same, the Streamer app fails when I try to do a Stream In. Looking at the code for the streamer app, it doesn't look like it checks the value of the data. I've also probed the flags, and they don't look significantly different from when I use the original code.
Can anyone give me some advice about what may be going wrong, or how to debug this? Is it possible that the VHDL code is less up to date, and I may have better luck with the verilog code? Is there some other example or documentation that anyone can recommend other than AN65974 that may help me?