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Hi all,
I am working cypress fx-3. I need change Input pins in GPIF II Slave FIFO. Currently all pins are configured as active low. But need to change SLWR,SLOE,PKEND pins should be in Active High. is it possible to change? and is it works? as normal.
Solved! Go to Solution.
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Hello Thrimurthi,
Yes, you can change SLWR,SLOE,PKEND pins polarity using GPIF-II Designer Tool.
To configure SLWR pin as a active high,right-click on the SLWR in the I/O Matrix Configuration diagram,click Input Signal Settings. as shown in the following figure.
Polarity: The assertion from the state machine can make the signal low or high depending on this setting.
Regards,
Anil Srinivas.
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Hello Thrimurthi,
Yes, you can change SLWR,SLOE,PKEND pins polarity using GPIF-II Designer Tool.
To configure SLWR pin as a active high,right-click on the SLWR in the I/O Matrix Configuration diagram,click Input Signal Settings. as shown in the following figure.
Polarity: The assertion from the state machine can make the signal low or high depending on this setting.
Regards,
Anil Srinivas.
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Hi all,
I am getting Data (incremental data) from FPGA as a master and Cypress as 8 bit slave FIFO.
Given configuration as flow,
#define CY_FX_FIFOLP_DMA_BUF_COUNT (8)
#define CY_FX_FIFOLP_DMA_RX_SIZE (0)
dmaCfg.prodSckId = CY_U3P_PIB_SOCKET_0 ;
dmaCfg.consSckId =CY_U3P_UIB_SOCKET_CONS_2 ;
apiRetStatus = CyU3PDmaChannelCreate (&glChHandleSlFifoPtoU, CY_U3P_DMA_TYPE_AUTO, &dmaCfg);
In Every 512 bytes of data 16 bytes are missing in a DMA buffer. I Getting 0x0000 to 0x00FF ( in first buffer) and 0x0114 to 0x0213( second buffer) I between 2 - 512 bytes if data 16 bytes is missing. I attached the control center Receiving data screen shot.
Thank You.
With Best Regards,
Thrimurthi m
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Hello Thrimurhthi,
--You have recieved full 512 Bytes of data (1F0(496)+16=512). Please see the following marked row in screenshot.
Regards,
Anil Srinivas.