fx2lp receives zeros from FPGA !!!

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Anonymous
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Hello 
I have altera cyclon V Soc DE1 and cypress cy7c68013a usb board FX2LP.
My project is send streaming data (counter from 0000 to FFFF) from FPGA to FX2LP.
After I connect data pins,flags,control signals and clock between FPGA and FX2LP ,FX2LP receives zeros , but when I connect data pins of FX2LP to 3.3V pin , the FX2LP pins receives high( 1 ).

   

I am using stream IN VHDL code from AN61345 project in http://www.cypress.com/documentation/application-notes/an61345-designing-ez-usb-fx2lp-slave-fifo-int...  , and I modified PLL, DDR and Pins assignment for CycloneV ( because AN61345  using Xilinx Spartan 6 FPGA) . 
 Can anyone help me to know where is the problem??

   

Thanks,,,

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1 Reply
Anonymous
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Hi,

   

Can you please use a scope and see if the data lines are all zeros? If so, please check your connection. Also verify the data sent from the FPGA

   

Regards,

   

-Madhu Sudhan

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