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USB Low-Full-High Speed Peripherals

Anonymous
Not applicable

1)Hardware enviroment

   

 Our board use CY7C68013A as synchronouse slave fifo, and a fpga as master.

   

CY7C68013A's CLKOUT at 12MHz, and FPGA's PLL use as input, output 40Mhz as CY7C68013A's IFCLK.

   

EEPROM is blank.

   

2)firmware and modification

   

use Cypress Suite USB 3.4.7\Firmware\Bulkloop example,  and only modify BulkLoop.c as follow:

   

 

   

   // CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

   

   // CPUCS = (CPUCS & ~bmCLKSPD) |bmCLKSPD0; //24MHz

   

    CPUCS = CPUCS & ~bmCLKSPD ;  //12MHz CLKOUT

   

 

   

   // set the slave FIFO interface to 48MHz

   

   //IFCONFIG |= 0x40;

   

   IFCONFIG = 0x03; //slave fifo, sync, external

   

3)host pc

   

   windows 7 32bit. 

   

   Cypress Suite USB 3.4.7

   

  CY3684_EZ-USB_FX2LP_DVK

   
     4)Running result   
   
      When board first plug in, enumerate ok. We can find Cypress EZ-USB FX2LP No EEPROM(3.4.5.000).   
   
      Use Cyconsole download BulkLoop.hex to CY7C68013A, re enumerate fail.   
   
      We can only find a "Unknown Device" in windows device manager. In the device property, can't find anything   
   
      about VID and PID.    
   
      We run bus hound, can capture the first enumerate, but no packet about the second enumerate.   
   
        
   
    Any tip will be wellcome.   
   
    Thanks a lot!   
   

 

   
        
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4 Replies
Anonymous
Not applicable

 Hi,

   

Can you please attach the screenshot of the error message shown in devcoe manager (right click on the device with exclamation, select 'Properties' and select General tab and Details tab)? What is the VID/PID being shown in dev manager? Also please attach teh USB trace that you analyzed.

   

 

   

Regards,

   

Gayathri

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Anonymous
Not applicable

 1) project ,source code and hex of Bulkloop

   

Bulkloop-2012-12-25.rar

   

2)We capture the screen about the first enumeration and the second enumeration.

   

test_cy7c68013a_First_enumeration.rar

   

test_cy7c68013a_Second_enumeration.rar

   

3)Bushound log information, mark the first and second enumeration log

   

CyConsole_log_information.txt

   

 

   

We change register config value in file BulkLoop.c as following:

   

   

   CPUCS = (CPUCS & ~bmCLKSPD) |bmCLKSPD0; //24MHz

   

   //CPUCS = CPUCS & ~bmCLKSPD; //12MHz

   

   ...

   

   

   //IFCONFIG |= 0x40;

   

   //IFCONFIG = 0x03; //slave fifo, sync, external

   

   IFCONFIG = 0xc3; //slave fifo, sync, internal

   

   
    and measure CLKOUT frequency, after download, it changed from default 12Mhz to 24MHz.   
   
    So we are sure the firmware is running.   
   
        
   
    Use internal 48MHz clock for IFCLK, so CY7C68013A not need FPGA's pll clock.   
   
        
   
    Thanks for your echo.   
   
        
   
    Eerry Christmas!   
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Anonymous
Not applicable

 We find what the question is. On our board, Wakeup is connected to GND via a resister.

   

So if we only enable DPEN in register WAKEUPCS, Buckloop.hex Renumerate successfully.

   

 WAKEUPCS    =0x04;  //ok

   

But if we enable WUEN and seletect WUPOL=0, fail again. 

   

WAKEUPCS    =0x05;  //fail.

   

It's strange thing.  We wakeup assert always, Renumerate fail. Why?

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Anonymous
Not applicable

 Hi,

   

 

   

Once the device has entered suspend mode, in order to exit the state through one of of the WAKEUP pin sources, it needs a FALS to TRUE transition on one of the enabled WAKEUP pin sources for it to assert wakeup interrupt.

   

 

   

Regards,

   

Gayathri

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