Hi
I am experimenting with FX2LP device, which is connected to an FPGA. I generate cca. 24MB/s data load. With streamer program (c#) it was great, the speed was excellent >30MB/s. Then I noticed that the load is not coherent, it is bursty. It depends on the settings of packet / transfer and transfer / queue. For example for 64 pac/xfer - 64 xfer/que i get 1 - 2ms when the queue is empty and the c# program refills it. The endpoints were configured as Bulk
The problem is that it is no additional RAM connected to FPGA, so it will be great if the load will be more coherent. (There won’t be the 1 - 2 ms gaps).
So I had an idea, but I don’t know if it is supported by the driver:
It is possible to double buffer the queue? So when the first is empty, the second is already started. Then there won’t be any gaps, and the transfer will be smooth.
Thank you
