USB Low-Full-High Speed Peripherals

We are using a third-party configurable HID board which uses the CY7C64215. I would like to integrate this function onto our own board, which will need support for at least 5 years. Is the CY7C64215 still a good choice for this, or should we use a newer IC?

Our application is only 8 buttons and 2 analog inputs which need to be used as USB HID devices.

Thanks!

What is the power consumption of the FX2LP18  when held in reset for both the three different supply inputs? I am working on a very power sensitive design and the USB will only be needed when powered externally. When in battery mode, I want to minimize the power consumption as much as possible by holding the part in reset (or even adding a power switch if necessary). The datasheet shows Isusp current, but it is not clear which power rail that is referring to. Also, it's not necessarily the same as when the part is in reset.

Hi

Does the CY7C65215A Linux API provide a method for i2c stuck bus recovery?  i.e. if a device connected to the master is holding the SDA line low can the CY7C65215A clock out the slave device so that it releases SDA?

Thanks

Mal

Our product based on cy7c68013a.

Most of them are Normally operating well. But some product did not be recognized about 2~3 times out of 10.

Power source, reset timing, i2c clk, data lines were good. However,there was someting very strange about i2c data voltage abnormal.

There was no pull up, or data transaction, but voltage level about 1.4v with pull down sometimes.(our voltage level 3.3v)

I haven't seen this symptom. Would you tell me how to debug this symptom? Wold you tell me how to solve this problem?

Hello,

I would like clarification on certain comments made in this post:

https://community.cypress.com/t5/USB-Low-Full-High-Speed/cy7c65215-jtag-pin-types-and-connections/m-p/110083

#1: Are pullups/pulldowns REQUIRED on the JTAG pins, or just SUGGESTED? If required, please confirm which pins get pullups/pulldowns.

#2: @YatheeshD_36 makes the comment: "Once SCB 1 is configured as JTAG the other interface in CY7C65215 cannot be used." This is NOT my understanding. I thought the restriction was that SCB 0 and SCB 1 could not be used concurrently. Please clarify, as this will severely affect my design.

#3: (unrelated to the referenced post): In the datasheet, revision M (https://www.cypress.com/file/129956/download) table 17 shows that SCB1 Mode 7 (JTAG) has TDO as pin 5, and TDI as pin 6. In prior versions, these two were swapped. Please also confirm that revision M is correct.

Thank you.

Hi,

We’ve got a realtime GPIF-based application, and we would really appreciate clarification on one point.

Does the flow state test the transaction counter?  Our waveform deliberately never enters the IDLE state, and yet it is stopping anyways when the TCB reaches zero.  How is this possible?

Thank you,

-Peter Iannucci