USB low-full-high speed peripherals Forum Discussions

Hi there,

Quick question regarding the CY7C65215:

I am using this device in USB-UART CDC Mode on SCB0, and USB-I2C Vendor mode on SCB1.  SCB1 appears to be working fine using the I2C mode using Vendor protocol (we are using it to configure/program a CCG4 device).

The CY7C65215 appears as 3 devices in the Device Manager under Universal Serial Bus Controllers:

• USB-Serial (Dual Channel) Vendor 1 (USB-I2C Vendor Interface?)
• USB-Serial (Dual Channel) Vendor MFG (Manufacturer Configuration Interface?)
• USB-Serial Adapter (I assume this is the UART CDC Interface)

Where I'm having a problem is using SCB0 as a COM port in Windows.  I need to be able to use with SCB0 as a COM port from a terminal, but I can't seem to find a way to do so.  In Device Manager, which driver should I be using to be able to use this interface as a COM port?  I have a number of possible folders containing USB-Serial drivers in the Cypress directory that I've accumulated through various different parts and eval kits:

• Cypress USB-Serial Driver
• CYUSB234 DVK
• EZ-USB FX3 SDK
• USB-Serial Driver
• USB-Serial SDK

Which one of these drivers should be installed to use SCB0 as a COM port?

Hi,   

     请教一个技术问题关于赛普拉斯 CY7C68013的问题，PCB Layout的时候如附件截图的数据总线和地址线需不需要做等长处理？ 是否此款芯片只有USB2.0的DP&DN管控一下等长和阻抗？附件截图请参考，谢谢。

Hello

My customer is using CY7C65211A as USB-SPI master on Linux.

They have some question like the following.

When isCypressDevice() is called thru printListOfDevices(), this seem to have a memory leak.

Deription :

if System board is connected with good device (as Cypress CY7C65211A) and called CyOpen(),

System board seems to be good working with CyClose() as rStatus == CY_SUCCESS.

but, if System board is called CyOpen() (as No device), it seems to have a memory leak.

if CY_ERROR_DRIVER_OPEN_FAILED as return value thru CyOpen() is repeated infinitely,
They would like to know if there can be happened a memory leak as symptom. also, if yes, could you please let me know method to solve memory leak?

Regards,
Jake

Hi.

I' am using this board with Yaselan Km512  printer.

and getting this message last days :

"[401100E7] the contents of eeprom error eeprom configuration did not complete "

I think it has CY3684.

Does anyone have an idea about error message and where can I find latest CY3684 latest XP drivers.

I couldn't install it with devtools files...

I referred AN75705  -Getting Started with EZ-USB® FX3™     I followed chapter 8 My First USB 3.0 Transfer Using FX3   

I have error during building the project

Regards

Esakki

您好，

客户目前需要选型USB3.0的外设控制器，推荐给客户型号是： CYUSB3014，客户查看资料后，不希望进行编程，类似找一款类似FT601的芯片，请问下CYUSB3014可以提供给客户现成的固件吗？客户不需要再进行编程了，

谢谢

hello，my firmare both Hsspeed and SSspeed can support multi frames well in windows. however, in linux under the Ssspeed mode multi frame can be emunerated and used well,but under Hsspeed only the frame index number is 1 can be used.is there any special changes need to be take in Hsspeed under linux?

What camera resolution is supported by the FX2LP with a camera frame rate of 25 to 30fps, is 2MP camera resolution supported?

I intend to stream video from the camera module to an android device, is a driver necessary?

Hi,

I am currently transferring about 4 MB per second with a Slave FIFO design and BULK transfers.

I use multiple transfers that are pipelined (overlapping) and writing into large buffers, so I get an error free transfer even if Windows is stalling the main software for a few seconds.

Now I want to transfer an additional data channel with the same device. The data packets received by the Slave FIFO are too large in order to buffer whole packets before then multiplexing them to the FIFO inputs.

I thought about doubling the FIFO clock and alternating the data onto the FIFO input pins, but then I would have to disentangle/demultiplex the alternating bytes in software which is an unwanted load on the processor.

So I had the idea to do as thought of above, but also alternating the FIFO address, so that I could actually demultiplex the data directly after them entering the chip.

While the FIFO address setup and hold times are a bit higher than the other ones, they should fit with an 8MHz write frequency.

At the moment I use EP6 with Autoin activated and all I have to do ist setup all the transfers in the queue, submit them, receive the data and resubmit the finished transfers.

I would switch the FIFO adddress to EP2 for the other data stream, setting up EP2 just the same way that EP6 is setup currently (I have used only half the FIFO buffer memory, so that should be possible).

If I now setup and submit the transfers for EP2 in the same way, could I then get synchronous transfer on both EPs?

Regards,

Frank