USB low-full-high speed peripherals Forum Discussions

What is the undershoot tolerance for CY7C65213? Not listed in Absolute Max.

I often see the description of -0.5V on other devices.
For example, the FX2LP datasheet describes "-0.5V to + 4.0V".
https://www.cypress.com/file/138911/download

Thank you,
Tetsuo

Hi,

I ‘ve another strange issue with my FX2LP18.

In GPIF mode used to download FPGA. I attached you my config (Cypress GPIF designer project and the associated gpif.c – slightly modified for SDCC).

Tu sum up : The EP2 is used as the Fifo Write in GPIF.

The software sent the FPGA bitstream over EP2 using XferData.

Everything works perfectly onto numerous USB port.

But, onto one USB port, the GPIF does not seems to work. Hangs … Seems it starts (I can see waveform onto FPGA side) but suddenly stops ...

Changing the size of Chunks of data being send to the FIFO EP2 seems to solve the issue.

Normally XferData sent chunks of 64ko.  If it send only chunks of 8ko it works (but it is slower ..).

But I assume there is something bad in my GPIF implementation.

The goal is send one 16 bits DATA with a control signal CS low as fast as possible.

The IFCLK clock is 48MHZ (and inverted and sent to the FPGA to respect SETUP time).

If you can look my code if it sounds OK for you …

Part of code that manage GPIF starts : (bFpgaLoadInProgress Boolean is true)

The GPIF count is set to the size (in word) of the FPGA bitstream (not visible here).

      // Handle OUT data...

      if(bFpgaLoadInProgress)               // if configuration process has started

      {

        if( GPIFTRIG & 0x80 )               // if GPIF interface IDLE

        {

          if ( ! ( EP24FIFOFLGS & 0x02 ) )  // if there's a packet in the peripheral domain for EP2

                  {

                        EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses Empty flag

                        SYNCDELAY;

                        GPIFTRIG = GPIFTRIGWR | GPIF_EP2;  // launch GPIF FIFO WRITE Transaction from EP2 FIFO

                        SYNCDELAY;

                        while( !( GPIFTRIG & 0x80 ) )      // poll GPIFTRIG.7 GPIF Done bit

                        {

                        }

                        FpgaLoadStatus = STICEX_CMD_FPGA_LOADING;                 //end of configuration

                  }

            }

      }

Thanks.

Hi,

I am using FX2LP kit with FPGA along with UVC implementation for displaying a video over VLC.
When I try to fetch data from FX2LP as a USB controller on USB control center, I am able to get fetch correct data from buffer.

But when I am using UVC framework with the same setting of worldwide = 0. I am getting less and wrong data in first data fetch. I have checked this using wireshark. Also attaching a screenshot to elaborate my issue.

In this image my first packet data length should be of 16380 bytes instead of 16028 bytes and starting of data is also wrong.

Is there some additional setting that I should do in case of UVC implementation?

Hello everyone ,

I'm currently working with an ezusb FX2 board and we are using an old firmware downloaded by the 32bits driver ezloader.sys i'm working on using the component with a 64bits processor. The problem is that i dont know how to get the firmware . I would like to read the ram of the component to retireve it after loading it in the board with the 32bits computer.  I will then load it using CyControlCenter on the 64bits computer if i can read the ram and get the firmware as an .hex maybe .

Thanks for your help.

Hi all,

I am having a issue when connecting my device through optical USB. The device communicates with PC via CyPressUsbSerial API via I2C. For normal USB connection it works, but it fails when I connect it to optical USB, the API fails to open I2C device, but I am able to see it on device manager.

The part number  is CY7C65215-32LTXI

Any suggestion on what should I try? Thanks

Hi everyone,

I'm a beginner and I'm looking for tips concerning how to about programming a cypress cy7c64225-28pvxct chip (used as a usb peripheral) and the atmega ųC for example.

Thanks guys !

hi,

After device re-enumeration, an user app downloads a new similar special purpose .hex file which slightly  different BULK endpoint configuration. How using a vendor command or else, somewhat, make the  endpoints in the new .hex file available to the host application PC.?.

Hi All,

This thread is regarding SPI interface of CY7265211 (USB to SPI Bridge). As per the datasheet of this part (CY7C65211/CY7C65211-A, USB-Serial Single-Channel (UART/I2C/SPI) Bridge with CapSense® and BCD (cypress.com)), this part supports standard SPI interface with following pins:

SCLK, Chip Select, Data Out, Data IN

Please let me know if we can configure this part in Quad SPI master mode with following pins:

SCLK, Chip Select, IO0 (MOSI), IO1 (MISO) and two other GPIO lines configured as data lines (IO2 and IO3) to connect with SPI Config Flash. We are planning to use SPI Flash from Cypress/Infineon (Part Number: S25FL128SAGNFI001).

Please help in providing the information ASAP.

Thanks & Regards,

Sunny Watts

Hi all,

I have a following problem:

I am using FPGA Spartan 6-cy7c68013a interface. Master FPGA sends the data from 1st to 2048th byte to EP6 (Bulk transfer, slave FIFO, 2048 bytes depth). I wrote a program on Visual Studio that requests the data from cypress EZ-USB device's FIFO.

The problem is that most of the times data packet is right:
1-2-3-4-5-6-7.....-2047-2048.

However, sometimes the format of the packet is wrong, parts of packet are swapped:

430-431-432-.....-2047-2048-1-2-3...428-429.

And the begging data is always random: it can be 430, 110 or anything. But, the cycle is always complete and all the set of data values (from 1 to 1024) is transferred. 

What can be the problem? Can anyone help to resolve it?