USB low-full-high speed peripherals Forum Discussions

i'm using the slave FIFO interface for bulk auto-in transfers directly from an FPGA to the host, in asynchronous mode.

Right after the FULL flag asserts, the FULL flag deasserts and the EMPTY flag asserts simultaneously.

I have attached a screen shot of the waveforms.

Any ideas of what could cause this?

Hi,
In my project based on cy7c68013a I need from time to time to switch endpoint EP2 direction from OUT
to IN and vise versa.
I do it through the following steps:

void TD_Init(void)             // Called once at startup
{
    CPUCS = 0x10;                 // CLKSPD[1:0]=10, for 48MHz operation, disable CLKOUT
    SYNCDELAY;                    // see TRM section 15.14

    IFCONFIG=0xcb;       
    SYNCDELAY;                    // see TRM section 15.14
    REVCTL=0x03;
    SYNCDELAY;                    // see TRM section 15.14

//EndPoints

    FIFORESET=0x80;
    SYNCDELAY;                   
    FIFORESET=0x82;
    SYNCDELAY;                   
    FIFORESET=0x84;
    SYNCDELAY;                   
    FIFORESET=0x00;
    SYNCDELAY;                   

    EP1OUTCFG = 0xA0;
    SYNCDELAY;                    // see TRM section 15.14
    EP1INCFG = 0xA0;
    SYNCDELAY;                    // see TRM section 15.14

    EP2CFG=0xa2;        //valid, out, bulk, 512, 2 x buff
    SYNCDELAY;
     EP4CFG=0xa0;        //valid, out, bulk, 512, 2 x buff
    SYNCDELAY;

    EP6CFG=0x00;        //invalid
    SYNCDELAY;
    EP8CFG=0x00;        //invalid
    SYNCDELAY;                   

    OUTPKTEND=0x82;
    SYNCDELAY;                   
    OUTPKTEND=0x82;
    SYNCDELAY;                   
    OUTPKTEND=0x84;
    SYNCDELAY;                   
    OUTPKTEND=0x84;
    SYNCDELAY;                   

    EP2FIFOCFG=0x18;    //AUTOIN,AUTOOUT,8-bit data bus
    SYNCDELAY;
    EP4FIFOCFG=0x00;    //manual, 8-bit data bus
    SYNCDELAY;

//to define buswidth==8-bit for all EP (disabled too !!)
    EP6FIFOCFG=0;    //8-bit data bus
    SYNCDELAY;
    EP8FIFOCFG=0;    //8-bit data bus
    SYNCDELAY;

    EP2BCL = 0x80;                // arm EP2OUT
    SYNCDELAY;                   
    EP2BCL = 0x80;
    SYNCDELAY;                   

    EP4BCL = 0x80;                // arm EP4OUT
    SYNCDELAY;                   
    EP4BCL = 0x80;   
    SYNCDELAY;

//Flags
    PINFLAGSAB=0xc8;    //FlagB - Full for EP2; FlagA - Empty for EP2
    SYNCDELAY;
    PINFLAGSCD=0x04;    //FlagD - PA7                     ; FlagC - Prg. for EP2
    SYNCDELAY;
    FIFOPINPOLAR=0x00;
    SYNCDELAY;

//Port D
    OED=0xff;         //OutputEnable port D (1-output, 0-input)
    IOD=0x00;         
}

void TD_Poll(void)              // Called repeatedly while the device is idle
{
    unsigned char tmp;

    if(!(EP2468STAT & 0x04))
    {
        tmp=EP4FIFOBUF[0];

        SYNCDELAY; 
        OUTPKTEND=0x84;
        SYNCDELAY; 
        OUTPKTEND=0x84;
        SYNCDELAY; 

        IOD=tmp;

        if(tmp==0x01)         //switch EP2 to IN
        {
            SYNCDELAY;                   
            FIFORESET=0x80;
            SYNCDELAY;                   
       
            SYNCDELAY;
            EP2CFG=0xe2;        //valid, in, bulk, 512, 2 x buff
            SYNCDELAY;

            FIFORESET=0x80;
            SYNCDELAY;                   
            FIFORESET=0x82;
            SYNCDELAY;                   
            FIFORESET=0x00;
            SYNCDELAY;           
           
            INPKTEND=0x82;
            SYNCDELAY;       
            INPKTEND=0x82;
            SYNCDELAY;       
   
            EP2FIFOCFG=0x18;    //AUTOIN,AUTOOUT,8-bit data bus
            SYNCDELAY;
            EP2AUTOINLENH=0x02;
            SYNCDELAY;
            EP2AUTOINLENL=0x00;

            EP2BCH=0x00;
            SYNCDELAY;       
            EP2BCH=0x00;
            SYNCDELAY;                   
            EP2BCL=0;
            SYNCDELAY;                   
            EP2BCL=0;
            SYNCDELAY;                   
        }
        else             //switch EP2 to OUT
        {
            SYNCDELAY;
            EP2CFG=0xa2;        //valid, out, bulk, 512, 2 x buff
            SYNCDELAY;
            SYNCDELAY;
        }
    }
}

Thus, I use EP4 (BULK, OUT, 512x2, MANUAL MODE, 8-bit) for switching EP2 (BULK, OUT, 512x2, AUTO MODE, 8-bit) direction and at the same time for changing status of pin D0 for its use by external device.
My question: why after switching from OUT to IN the FULL FLAG always becomes active (low)?

Thank you for your help
Victor

I want to know what exactly is the format of IIC files. Like is it in a HEX format or binary format. And I would also like to know how exactly the conversion happens from HEX file to IIC file. I need to add a routine to calculate checksum for an IIC file, is it possible ?

i get to know

00000000  c2 47 05 31 21 00 00 04  00 04 00 00 02 32 81 32
 

    
• c2: boot byte, poke eeprom content to ram
    
• 3 x 2 bytes of vid, pid, did (here: set by firmware)
    
• 04: config byte, connected, 48 mhz, not inverted, 100 khz i2c
    
• 00 04 00 ...: should be first firmware bytes
   

 00003450  d6 00 02 10 d6 00 02 10  d6 00 80 01 e6 00 00

    
• e6 00 00: reset command, 0xe600 is the cpucs addr
   

Please help me out with this !!!!!!!!!!!!

Best Regards,

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i download the CYStream_RefDesign file,and use the CyUSB.inf,when i install the inf file,it remind me error code 10.now am confuse.thanks