USB low-full-high speed peripherals Forum Discussions
I'm trying to use the CyAPI.lib with VC++ 6.0, and when I compile, I get the following errors:
Linking...
CyAPI.lib(CyAPI.obj) : error LNK2001: unresolved external symbol ___security_cookie
CyAPI.lib(CyAPI.obj) : error LNK2001: unresolved external symbol @__security_check_cookie@4
CyAPI.lib(CyAPI.obj) : error LNK2001: unresolved external symbol ___CxxFrameHandler3
CyAPI.lib(CyAPI.obj) : error LNK2001: unresolved external symbol __EH_epilog3
CyAPI.lib(CyAPI.obj) : error LNK2001: unresolved external symbol __EH_prolog3
CyAPI.lib(CyAPI.obj) : error LNK2001: unresolved external symbol __EH_epilog3_GS
CyAPI.lib(CyAPI.obj) : error LNK2001: unresolved external symbol __EH_prolog3_GS
Debug/cybulk.exe : fatal error LNK1120: 7 unresolved externals
What is causing this? I'm trying to simply compile the examples that came with the CyAPI.lib (CyBulk in this case).
Thanks,
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I am using the .NET dll from SuiteUSB to interface with a FX2LP. In my PC application I am calling the BulkInEndpt.Xferdata method at an interval of about 1 second.
My driver is not signed or self signed. I use 64 bit version. I know that I must sign this driver but I was unable to do so.
Signtool give me unexpected error "CertOpenStore() failed". I am wating the signing of driver: this must be done by a colleague.
As a result the device is not seen as Plug and Play, even if I use F8 to force the use of unsigned driver.
The documentation makes it sound like the major reason the Xferdata function should return false is because of a timeout.
I have tried adjusting the timeout from 1000ms to 100000ms to see if the driver is simple slow for some reason.
I have used C# driver command to see if the Driver see the firmware correctly.
I have compared the data given in the console application by C# driver meber of CyUsbDevice with data of firmware: they match perfectly. So the error is not here.
I noticed there are UsbdStatus and NtStatus members of the CyUSBEndPoint Class that contain error codes of the xferdata method.
I have used this members to obtain information about this errors.
URB status (from UsbdStatus command) is set to USBD_STATUS_CANCELED (0xC0010000).
This data is confirmed by Ntstatus code ( 0xC0000120 aka STATUS_CANCELLED) .
I am able to select the device using VID and PID (console application see if the device is attached or not).
From this data, it seems to me that the problem is lacking of Signing that prevents the correct behavior of driver.
Open the device is possible because use the data of DeviceObject created by Enumeration Process ( driver of the bus, not Device Driver).
Xfer data do not function because use Device Driver ( not Bus Driver), and Device Driver is not correctly charged even if I use F8 and select Charge Usigned Driver ( is not Plug and Play).
Windows Vista (and Windows 7) Plug and Play device installation requires driver packages to have a signed catalog file. Driver packages commonly consist of multiple files; the catalog file contains the signature for the entire package.
-Pavesi Sergio
Show LessHi there,
I wanted to know when we use manual mode, the flagb&c dont work is it? I am writing a test sequence from my master which is a PLD to the slave fifo (microcontroller cy7c68013a). I can see the test data in the endpoint buffer (of the slave) but the flags and byte counts always read empty! Has anyone come across this before?
Thanks in advance
Show LessHi
Sorry, my english is not well, but I will try to let you know my question.
Please kindly resolve my question or provide me some implications
Thank you very much.
I took a FPGA to connect CY7C68013A and then work in the Slave-FIFO mode.
I could successfully work on my PC of High-Speed support.
But today, I would like to connect older PC, whose only support USB1.1 or USB2.0 Full-Speed.
I could not link it by my device.
My PC and older PC were installed WinXP.
I do not know how to resolve this issue, could you please kindly provide me some solutions for me information
Thank you!!
Show Lessi'm using the slave FIFO interface for bulk auto-in transfers directly from an FPGA to the host, in asynchronous mode.
Right after the FULL flag asserts, the FULL flag deasserts and the EMPTY flag asserts simultaneously.
I have attached a screen shot of the waveforms.
Any ideas of what could cause this?
Show LessHi,
In my project based on cy7c68013a I need from time to time to switch endpoint EP2 direction from OUT
to IN and vise versa.
I do it through the following steps:
void TD_Init(void) // Called once at startup
{
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, disable CLKOUT
SYNCDELAY; // see TRM section 15.14
IFCONFIG=0xcb;
SYNCDELAY; // see TRM section 15.14
REVCTL=0x03;
SYNCDELAY; // see TRM section 15.14
//EndPoints
FIFORESET=0x80;
SYNCDELAY;
FIFORESET=0x82;
SYNCDELAY;
FIFORESET=0x84;
SYNCDELAY;
FIFORESET=0x00;
SYNCDELAY;
EP1OUTCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP1INCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP2CFG=0xa2; //valid, out, bulk, 512, 2 x buff
SYNCDELAY;
EP4CFG=0xa0; //valid, out, bulk, 512, 2 x buff
SYNCDELAY;
EP6CFG=0x00; //invalid
SYNCDELAY;
EP8CFG=0x00; //invalid
SYNCDELAY;
OUTPKTEND=0x82;
SYNCDELAY;
OUTPKTEND=0x82;
SYNCDELAY;
OUTPKTEND=0x84;
SYNCDELAY;
OUTPKTEND=0x84;
SYNCDELAY;
EP2FIFOCFG=0x18; //AUTOIN,AUTOOUT,8-bit data bus
SYNCDELAY;
EP4FIFOCFG=0x00; //manual, 8-bit data bus
SYNCDELAY;
//to define buswidth==8-bit for all EP (disabled too !!)
EP6FIFOCFG=0; //8-bit data bus
SYNCDELAY;
EP8FIFOCFG=0; //8-bit data bus
SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
EP4BCL = 0x80; // arm EP4OUT
SYNCDELAY;
EP4BCL = 0x80;
SYNCDELAY;
//Flags
PINFLAGSAB=0xc8; //FlagB - Full for EP2; FlagA - Empty for EP2
SYNCDELAY;
PINFLAGSCD=0x04; //FlagD - PA7 ; FlagC - Prg. for EP2
SYNCDELAY;
FIFOPINPOLAR=0x00;
SYNCDELAY;
//Port D
OED=0xff; //OutputEnable port D (1-output, 0-input)
IOD=0x00;
}
void TD_Poll(void) // Called repeatedly while the device is idle
{
unsigned char tmp;
if(!(EP2468STAT & 0x04))
{
tmp=EP4FIFOBUF[0];
SYNCDELAY;
OUTPKTEND=0x84;
SYNCDELAY;
OUTPKTEND=0x84;
SYNCDELAY;
IOD=tmp;
if(tmp==0x01) //switch EP2 to IN
{
SYNCDELAY;
FIFORESET=0x80;
SYNCDELAY;
SYNCDELAY;
EP2CFG=0xe2; //valid, in, bulk, 512, 2 x buff
SYNCDELAY;
FIFORESET=0x80;
SYNCDELAY;
FIFORESET=0x82;
SYNCDELAY;
FIFORESET=0x00;
SYNCDELAY;
INPKTEND=0x82;
SYNCDELAY;
INPKTEND=0x82;
SYNCDELAY;
EP2FIFOCFG=0x18; //AUTOIN,AUTOOUT,8-bit data bus
SYNCDELAY;
EP2AUTOINLENH=0x02;
SYNCDELAY;
EP2AUTOINLENL=0x00;
EP2BCH=0x00;
SYNCDELAY;
EP2BCH=0x00;
SYNCDELAY;
EP2BCL=0;
SYNCDELAY;
EP2BCL=0;
SYNCDELAY;
}
else //switch EP2 to OUT
{
SYNCDELAY;
EP2CFG=0xa2; //valid, out, bulk, 512, 2 x buff
SYNCDELAY;
SYNCDELAY;
}
}
}
Thus, I use EP4 (BULK, OUT, 512x2, MANUAL MODE, 8-bit) for switching EP2 (BULK, OUT, 512x2, AUTO MODE, 8-bit) direction and at the same time for changing status of pin D0 for its use by external device.
My question: why after switching from OUT to IN the FULL FLAG always becomes active (low)?
Thank you for your help
Victor
Will an encore II part show up on the USB as unprogrammed... like an FX2 part does?
Hi,
I am trying to speed up my FX2 firmware and trying to clean up the code. I found that SYNCDELAY macro is used very often in my code and also in firmware examples given by Cypress. For example, code below is taken from C:\Cypress\Cypress Suite USB 3.4.7\Firmware\Bulkloop\bulkloop.c
... EP2CFG = 0xA2; SYNCDELAY; EP4CFG = 0xA0; SYNCDELAY; EP6CFG = 0xE2; ...
As far as I understand from TRM sections 15.15, such a delay should be used in situation when you write some register A then read/write other register B and register B depends in some way on register A. This delay just gives a time for internal hardware to "catch" new value & update all others that depend on it.
So in the given example because we only write registers, there is no need for such delays, right? Please correct me if I am wrong.
Best regards, Arturas
Show LessI want to know what exactly is the format of IIC files. Like is it in a HEX format or binary format. And I would also like to know how exactly the conversion happens from HEX file to IIC file. I need to add a routine to calculate checksum for an IIC file, is it possible ?
i get to know
00000000 c2 47 05 31 21 00 00 04 00 04 00 00 02 32 81 32
- c2: boot byte, poke eeprom content to ram
- 3 x 2 bytes of vid, pid, did (here: set by firmware)
- 04: config byte, connected, 48 mhz, not inverted, 100 khz i2c
- 00 04 00 ...: should be first firmware bytes
00003450 d6 00 02 10 d6 00 02 10 d6 00 80 01 e6 00 00
- e6 00 00: reset command, 0xe600 is the cpucs addr
Please help me out with this !!!!!!!!!!!!
Best Regards,
Show LessI am using the Slave FIFO to do bulk transfers from the host to an FPGA. When I send a packet from the host I am able to read the expected number of bytes from the Slave FIFO. However instead of the expected data I get an alternating sequence of bytes. Further, there are 2 sequences, which alternate with each packet sent.
For example:
And so on.
The endpoint is double buffered, so maybe it switches between sequences when the buffer changes?
I verified with a USB analyzer that the packet sent to the FX2LP is correct.
Any ideas why I get these symptoms?
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