USB low-full-high speed peripherals Forum Discussions

I am new to this field, so just learning........

Below is the firmware code  please correct it if any mistake is there.

void TD_Init( void )

{ // Called once at startup

  CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

  /*1 0010  48MHz, CLKOUT pin driven*/

  IFCONFIG = 0xCB; // for async?  IFCONFIG

  /*1100 1111  Internal default clk, 48MHz,async , slave fifo interface*/

  SYNCDELAY;                    // see TRM section 15.14

  EP2CFG = 0xA2;                // BUF[1:0]=10 for 2x buffering

  /*Endpoint 2 Configuration 1010 0010*/

  //bit 7 1 to activate an end point

  //bit 6 0 OUT

  //bit 5 1

  //bit 4 0  Bulk(default)

  //bit 3 0 512 bytes

  //bit 2 0

  //bit 1 1  double

  //bit 0 0

  // EP6 512 BULK IN 2x

  SYNCDELAY;                    //

  EP6CFG = 0xE2;                // BUF[1:0]=10 for 2x buffering

  /*1110 0010*/

  //bit 7 1 to activate an end point

  //bit 6 1 IN

  //bit 5 1

  //bit 4 0  Bulk(default)

  //bit 3 0 512 bytes

  //bit 2 0

  //bit 1 1  double

  //bit 0 0

  // EP4 and EP8 are not used in this implementation...

  SYNCDELAY;                    //

  EP4CFG = 0x20;                // clear valid bit 10 0000

  //bit 7 0 to deactivate an end point

  //bit 6 0 OUT

  //bit 5 1

  //bit 4 0  Bulk(default)

  //bit 3 0 512 bytes

  //bit 2 0

  //bit 1 0  quad

  //bit 0 0

  SYNCDELAY;                    //

  EP8CFG = 0x60;                // clear valid bit 0110 0000

  //bit 7 0 to deactivate an end point

  //bit 6 1 IN

  //bit 5 1

  //bit 4 0  Bulk(default)

  //bit 3 0 512 bytes

  //bit 2 0

  //bit 1 0  quad

  //bit 0 0

  SYNCDELAY;

  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

  SYNCDELAY;                    // see TRM section 15.14

  FIFORESET = 0x02;             // reset, FIFO 2

  SYNCDELAY;                    //

  FIFORESET = 0x04;             // reset, FIFO 4

  SYNCDELAY;                    //

  FIFORESET = 0x06;             // reset, FIFO 6

  SYNCDELAY;                    //

  FIFORESET = 0x08;             // reset, FIFO 8

  SYNCDELAY;                    //

  FIFORESET = 0x00;             // deactivate NAK-ALL

  // handle the case where we were already in AUTO mode...

  // ...for example: back to back firmware downloads...

  SYNCDELAY;                    //

  EP2FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=1

  // core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

  SYNCDELAY;                    //

  EP2FIFOCFG = 0x11;            // AUTOOUT=1, WORDWIDE=1  0001 0001 (16 bit)

  //bit 6 0  flag for synch fifo

  //bit 5 0  flag for synch fifo

  //bit 4 1 AUTOOUT buffer is automatically and instantaneously committed to the endpoint FIFO

  //bit 3 0 

  //bit 2 0

  //bit 1 0  

  //bit 0 1

  SYNCDELAY;                    //

  EP6FIFOCFG = 0x0D;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1  0000 1101(16 bit)

  //bit 6 0  flag for synch fifo

  //bit 5 0  flag for synch fifo

  //bit 4 0 

  //bit 3 1 AUTOIN buffer is automatically and instantaneously committed to the endpoint FIFO

  //bit 2 1 a zero length packet will be sent when PKTEND is activated

  //bit 1 0  

  //bit 0 0

  SYNCDELAY;

  PINFLAGSAB = 0xE0;                                          // FLAGA - indexed, FLAGB - EP6FF  1110 0000

  //bit 7 1  FLAGB3

  //bit 6 1  FLAGB2

  //bit 5 1  FLAGB1          (A8 priority 11 indicate Full)

  //bit 4 0  

  //bit 3 0 

  //bit 2 0

  //bit 1 0  

  //bit 0 0

  SYNCDELAY;

  PINFLAGSCD = 0x08;                                          // FLAGC - EP2EF, FLAGD - indexed  0000 1000

  //bit 7 0 

  //bit 6 0 

  //bit 5 0

  //bit 4 0  

  //bit 3 1  FLAGC3 - EP2EF (A0 priority 9 indicate Full )

  //bit 2 0

  //bit 1 0  

  //bit 0 0

  SYNCDELAY;

}

Above is the code for 16 bit Slave FIFO Interface, asynchronus mode.

For testing firmware, I am using Bulk loop program to send and receive data. And loop back  I am doing from 32 bit Atmel AVR micro controller at other end.

 While I send data through bulk loop program it is received properly at Atmel controller. But when I send data from Atmel (or write data from Atmel into the slave fifo ) data is coming properly at cypress chip(I checked through digital osciloscope) but the bulk loop program not showing any data.

Please have a look at firmware code for any mistake.

Thanks in advance……

Hello,everyone!

I am using GPIF write waveform to send less than 512 bytes data block.

I referenced Knowledge Base Article "NextData/ActivateData in the GPIF read Waveform Interval".

In this paper,

In order to write data from the FIFO to the external peripheral, you will do an activate data first in one interval. Doing this will result in driving the first byte in the FIFO on to the GPIF data bus and then you may do a Next FIFO Data on the subsequent interval. Doing an Activate Data and a Next FIFO Data on the same interval will result in incrementing the FIFO  pointer and driving the new data (pointed to by the incremented pointer) and should be done in subsequent intervals. Therefore a Next FIFO Data is required in case of GPIF Write

I activated data first in one interval(Same Data),and Next FIFO Data on the subsequent interval.

I writed 256 bytes “0x00, 0x01,…, 0xFF”,but read  data is 258 bytes “0x00, 0x01,…, 0xFF,0xFE, 0xFF”.

So , last 2 byte in the FIFO,” 0xFE ,0xFF” repeated.

What is the reason?

The source code is as following.

// we are just using the default values, yes this is not necessary...

TD_INIT()

{

             EP2CFG = 0xA2;                               //           double buffer,bulk

             SYNCDELAY;                   

…

EP2FIFOCFG = 0x15;                                      //00010101 : AUTOOUT=1, ZEROLEN=1, WORDWIDE=1

             EP2AUTOINLENH = 0x02;                    // When AUTOOUT=1, core commits IN data

             SYNCDELAY;

             EP2AUTOINLENL = 0x00;                     // ...when EPxAUTOINLEN value is met

             SYNCDELAY;

             EP2GPIFFLGSEL = 0x01;                    //           FiFo empty Flag

…

}

void TD_Poll(void)              // Called repeatedly while the device is idle

{

             if( GPIFTRIG & 0x80 )           // GPIF is Idle

             {

                           if(!(EP2468STAT & bmEP2EMPTY))

                           {

                                        GPIFTRIG = GPIFTRIGWR | GPIF_EP2;

                           }

…

}

}

In Waveform, I repeated “Next FIFO Data on the subsequent interval” until EP2GPIFFLG empty.

Hi

i'm searcing for FPGA configuring example in SuiteUsb 3.4.5 installation, but i cannot find the software FPGA configuration utilities and all code and firmware about this example

Someone can helpme?

Maybe have i  to use another revision of SuiteUsb.

Thanks in advance

Hi, in my design the FIFO is synchronously filled at aobut 6MBs, with streaming data coming from and ADC, with some glue logic in between (it's and SDR application). If I use isochronous endpoint with 1024 size packet and 1 packet per microframe, the bandwidth is roughly 8MBs. Since the USB side is faster than the FIFO side, it means (if I understood correctly, i'm new to USB) that some IN tokens will arrive when no data has been committed yet. What happens in this case? The host will wait or a zero packet length will be sent? 

I could shorten the isochronous packet length to match the bandwidths, 750 size packet gives 6MBs, but my understanding is that it is better to have a faster USB side, in order to avoid full FIFO event and loss of data (there is no other buffer in between). Am I correct?

One last question: when the FIFO goes from full to empty and the flag is de-asserted, is this flag change synchronous with IFCLK or it can happen asynchronously?

Thanks

I am doing a project in which we have to make a wireless USB joystick. I searched for various USB microcontrollers such as CY7C6300x and read the datasheet of it. Can anyone please tell me how to program this microcontroller or is there any other better microcontroller.

Hi, every one.

I'm using CY7C68013 to implement a data acquisition system.FPGA sends the data flow to the host via USB.The configuration of the USB is  as follows: EP2 IN, 512bit, quad buffers, slave fifo, auto in mode, and with an external IFCLK(24Mhz).The writting rate to endpoint is about 2.5MB/s.And the FPGA writes to the endpoint2 continuously unless it is not full.

The host program is based on .NET(C#) .To test transfer speed, i ordered my host to request for data repeat from 68013. The XferSize was set to 256KB,and the host requested for 256KB each time.But the host program occasionally broke down.It can happened during the anytime when executing Xferdata()(maybe the first time or even after 10 mins). The return NtStatus can be "0xC000 0120" or "0xC001 0000".And the string returned by UsbStatusString() was "[state=HALTED status=UNKNOWN]".

I don't know how to map these error codes to the real problems.It seems others seldom using .NET to implement a project. I checked my FPGA program,the firmware and the C# program.But i can't find anything wrong.Maybe I've missed or misunderstood something.Please help me.

Main part of the firmware and C# codes are as follows:

Firmware:

void TD_Init(void)             // Called once at startup
{
  IFCONFIG |= 0x03; //external clock from FPGA:24 Mhz
  SYNCDELAY;
  REVCTL = 0x03;   // 
  SYNCDELAY;
  EP2CFG = 0xE0; // IN, bulk mode,quad buffering,512bit each buffer   
  SYNCDELAY;

  FIFORESET = 0x80;  // reset all FIFO
  SYNCDELAY;
  FIFORESET = 0x82;
  SYNCDELAY;
  FIFORESET = 0x84;
  SYNCDELAY;
  FIFORESET = 0x86;
  SYNCDELAY;
  FIFORESET = 0x88;
  SYNCDELAY;
  FIFORESET = 0x00;
  SYNCDELAY;
 
  EP2FIFOCFG = 0x09; 
  SYNCDELAY;
  PINFLAGSAB = 0x00; // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
  SYNCDELAY;           PINFLAGSCD = 0x00; // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
  PORTACFG = 0x40;   // Enable SLCS
  SYNCDELAY;
  FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low
  SYNCDELAY;
  EP2AUTOINLENH = 0x02; // autoin length：512bit
  SYNCDELAY;     
  EP2AUTOINLENL = 0x00; 
  SYNCDELAY;
  EP2FIFOPFH = 0x90;// FLAGA: PKTSTAT = 0,PF asserts if committed packest are more than 2.
  SYNCDELAY;
  EP2FIFOPFL  = 0x00;
}

C# code

 int count = 0;
        CyBulkEndPoint bulkEndptOut;
        private void button1_Click(object sender, EventArgs e)
        {
            USBDeviceList usbDevices = new USBDeviceList(CyConst.DEVICES_CYUSB);
            CyUSBDevice MyDevice = usbDevices[0x04B4, 0x1004] as CyUSBDevice;
            if (MyDevice == null)
            {
                MessageBox.Show("No device attached！");
                return;
            }
            bulkEndptOut = MyDevice.EndPoints[1] as CyBulkEndPoint;
            if (bulkEndptOut == null)
            {
                MessageBox.Show("Can't find endpoint!");
                return;
            }
            bulkEndptOut.XferSize = 4096 * 64 ;// Set XferSzie 256KB
            Thread t = new Thread(new ThreadStart(subFun));
            t.Start();
         }
        bool bComplete = true;
        void subFun()
        {
            while (true) //for test only,it's a dead loop
            {
               
                int[][][] mData = new int[1][][];
                for (int i = 0; i < mData.Length; i++)
                {
                    int len = 256 * 1024;//requset  for 256KB each time
                    byte[] buf = new byte[len];
                    count++;
                    bComplete = bulkEndptOut.XferData(ref buf, ref len);
                }
            }
           
        }

I would like to use multiple configuration descriptors.  One of them would have a DirectSound interface (and that interface would not receive data from the Cypress driver), the other would not have that interface and instead the Cypress driver would provide the data that DirectSound would have using the vendor-defined interface.

I have added the extra configuration descriptor (and associated interface/endpoint descriptors) to dscr.a51.  I also modified SetupCommand(void) so that SC_GET_DESCRIPTOR / GD_CONFIGURATION (and GD_OTHER_SPEED_CONFIGURATION) will return the correct descriptors.  I also modified the ISR's Ures and Highspeed so that they correctly handle switching the configuration types from CONFIG_DSCR to OTHERSPEED_DSCR.

If I manully enter the commands for getting the DirectSound descriptor, I get back the correct descriptor.  However, when I send the command for setting the DirectSound descriptor, nothing happens; I don't see a DirectSound device and no data flows to the FX2.

When I look in the CyConsole or the USB Control Center, I can see two configurations, but they're both "configuration 1".  I know that my DirectSound config descriptor is set correctly - recall that get descriptor works fine, and shows configuration 2.

Do I need to disconnect and reconnect from the USB using USBCS in order for the new DirectSound configuration descriptor to be seen?  Why can't the Control Center or Console see the other configuration descriptor?

 Hi, all

Im working with a cmos sensor connected to the slave fifo of 68013, the frame sync signal of the cmos is captured by INT0. In the INT0 service routine, i want to insert some user defined bytes to the cmos data stream. My question is, how can i exactly know how many bytes are in the fifo now? Because the inserted bytes should not overwrite any cmos data that are already in the fifo. Can the EPxBCH:L register or Autopointer be helpful?

Thanks!