USB low-full-high speed peripherals Forum Discussions
The chip is 68013A.
We transfer data at speed 54MBps, I have tested the top speed of my board is about 32MBps. What I used is: EP6/AUTOIN/512*4 buffer/BULK mode. Do you have any methord to meet my data transfer speed need? Thanks for help.
Show LessThe chip is 68013A.
We transfer data at speed 54MBps, I have tested the top speed of my board is about 32MBps. What I used is: EP6/AUTOIN/512*4 buffer/BULK mode. Do you have any methord to meet my data transfer speed need? Thanks for help.
Show LessThe chip is 68013A.
We transfer data at speed 54MBps, I have tested the top speed of my board is about 32MBps. What I used is: EP6/AUTOIN/512*4 buffer/BULK mode. Do you have any methord to meet my data transfer speed need? Thanks for help.
Show LessThe chip is 68013A.
We transfer data at speed 54MBps, I have tested the top speed of my board is about 32MBps. What I used is: EP6/AUTOIN/512*4 buffer/BULK mode. Do you have any methord to meet my data transfer speed need? Thanks for help.
Show LessHello,
I'm new to cypress products. I'm willing to adapt a board with a Cy7C64013C USB controller to new specifications.
First thing first : I need to find a way of programming it. I havn't found the hardware connection to use in its datasheet.
Also, is there a developpement Kit suitable for this componant?
thanks in advance.
Cyril
Show LessWe using external logic control 68013A in slave FIFO mode , It connect with ARM9 by linux only in full speed mode. Now we have a problem . when we using ARM wirte 68013A ,the speed can reach 200K , but when we read ,the speed only 25k,too slow.
Can you give some advice,what the problem? the firmware ,the dirver(this dirver of linux were make by ourself) or something we need setting up for linux kernel.
Thank very much
Show LessHi,
I am using Cypress FX2LP in my interface design with Xilinx Spartan3 FPGA.. Based on Xilinx reference design schematics (from Digilent Nexys-3 Board and Xilinx Spartan3 Evaluation Kit), I found that VBUS from the USB connection may be left floating for self powered designs.
I left VBUS Pin from USB connector as "no connect" and connected wake pin of FX2LP on GPIO of FPGA. On the custom board, I found that FX2LP will not appear in the System Device list unless I pull the WAKE line HIGH from FPGA. Therefore, I pulled the FX2LP wake line high. Since then, I apparently had no problems with my design, except, once in a million times, I have to perform a power cycle as the device won't show in the system devices.
Recently, I came across Cypress AN15813, that states that monitoring the VBUS signal is very important and must be used in conjunction with wake line on FX2LP.
My Question is:
1- Is it mandatory to monitor VBUS line in self powered mode while using FX2LP in Slave FIFO Mode, I did not find such connectivity in XIlinx based Reference Designs?
2- Can FX2LP drive D+/D- lines if wake pin is driven high in Slave FIFO Mode, while nothing is driven by the FPGA controller on the data lines, and WAKE pin is pulled up?
Thanks,
Moazzam
Show LessI have a 3 button mouse working (with PSoC 1 device- CY8C24894), but I would like to add the wheel functionality to it. I would appreciate if anyone can share some info on this. I have modified the HID Template (for the 3 button mouse), but for some reason the mouse does not work at all with this configuration after modification, so I would assume that there is something wrong with what I am doing.
Show LessAre there any examples of I2C code for the 68013A that works in a multi-master environment. To be clear, I do not expect the 68013A to respond as a slave device.
From the TRM it looks like it should work, but there are a few questions.
What happens if there is a contention during the EEPROM boot load?
Does the I2C interface track the current state of the bus, i.e., if both the SCL and SDA lines are high and there has been a START without a STOP is the bus considered busy?
On page 190 of the TRM the BERR description says there is a deadlock condition. Assuming neither SCL nor SDA are stuck low will an externally synthesized STOP clear the bus?
Chris Rhodin
Aptina Imaging
Show LessI took a sample project and started modifying to implement a USB HID mouse. The basic functionality is working, although I would like to get the mouse wheel to work as well. The sample project did not contain the HID descriptor template for this. I tried to modify the HID descriptor using HID Template Editor, but when I edit and Apply, it disappears once I reopen again.
So, my question is how to edit the HID template (to add a new template or edit the existing one) using PSoC Designer?
Show Less