USB low-full-high speed peripherals Forum Discussions

 Hi i have question about flagD in slavefifo example. 

As document, flagD was using ep6 full flag. 

But i so confused this full flag's syntax meaning. 

As i know, ep6 is IN.

So if fx2's fifo is empty, why flagD is goto high transition?

Is high(0->1)meaning full? or empty?

Why flagD is goto high?

What is mean that the ep6 full flag go to high?

 Hello,

I am working on USB device, which receives data from Windows PC over USB and Tansmit data over ethernet lines to slave devices. My end points configuration is 

EP 2 - AUTOOUT, 2x Bulk, 512 Bytes

EP4 - AUTOOUT, 2x Bulk, 512 Bytes

EP6 - AUTOIN, 2x Bulk, 512 Bytes

EP8 - AUTOIN, 2x Bulk, 512 Bytes

My Cypress Chip is working in Slave FIFO Mode and Spartan 6 FPGA is acting as master. i am able to receive data on my host pc from usb device via end point 6 and 8 without any problem and i am able to transmitt data from host pc to usb device via end point 4 without any issue. Rx and Tx are working independently without any problem. 

But when i am doing bulk transfer on end point 2, the communication stops after 130 transmission of 512 bytes chunk. 

I have check data on USB Analyzer. I am not getting acknowledgement of my last transmitted packet. I have attached signals received on chipscope. 

Please help me solve this issue.

Recently, I have met a packet loss problem with the bulk asynchronous transfer from fpga to pc(16Mbps).

conf: bulk IN ; ept 6;  maxpacketsize = 512; slave fifo mode.

        with the data goes form 0x0000 to 0xffff as a cycle, I set the  asynchronous data get length once as 512 * 256. Data loss when the data number reach  0x8800

                                                      0x1088800

                                                      0x2088800

                                                      0x4088800 

                                                      0x8088800

                                                      0x9800000

attached are the firmware and my  asynchronous transfer code. 

Hi,

I would like to develop a firmware for our application. I am manipulating the bulk loop example code. One modification I need is to run the device in high speed mode(our device is fx2lp and is high speed capable). I modified the code this way:

There is a function named HighSpeedCapable(). I manipulated the code in such a way that it always returns true. but when I download the iic file on my device and open the cy console, I notice that the maximum packet size for endpoints is set to 64. I guess in the dscr.a51 file, the descriptor for full speed mode containts maximum packet size 64 and the device dscr table for high speed mode containts the value 1024. So what is wrong with that? does it mean it is not running in high speed mode though I have set the return vaule of HighSpeedCapable function to true?

I have another question : when I want to use the assembly directive " org (($ / 2) +1) * 2"  i get the error : bad relocatable expression. what is the problem?

Tnx

 In general, default firmware is loaded, which enumerates Cypress board with specific VID/PID. (04b4 : XXXX type)

I wish to load a short descriptor file from EEPROM, which helps bootloader to enumerate with my chosen VID/PID for loadinf firmware from host via USB. or am i forced to enumerate with Cypress VID/PID for USB boot ?

Thank you 

Iam working with the EzUSB driver since a long time. Now Iam switching to CyUSB Driver. Everything is working fine except reading data through EP1. With the EzUSB it was no problem to read/write the bidir EP1 since there are different IOCTL's for reading/writing and the driver handles the direction. I couldn't find this feature in the CyUSB driver because there is only the xx_SEND_NON_EP0_xx IOCTL. This is OK for EP2..EP8 since the direction is determined in the config but EP1 is BIDIR by nature, writing works perfect but reading doesn't..Question: is there any way to switch the direction of EP1?

I am using a cy7c68 usb controller. I am using a FPGA to simulate the behavior of an EEprom for cy7c68. I have successfully got C0 boot mode working. ( that is I have revised the inf file with th PID and VID that is stored on EEprom and the usb device is successfully recognized by the computer).

But I couldn't get C2 boot mode working. I have done as exactly as it is said in the document and when I verify the I2C signals they are all working properly that is when EEprom acknowledges C2 boot mode, cy7c68 starts to read the specified bytes and at the end of the data record I assert the specific bytes required to bring 8051 out of reset. but the usb device is not recognized by the computer. Is there anyway to debug the problem? or maybe I have missed out an action required to get 8051 working? ( such as using the "wake up" pin!!?) . as I said when I inspect I2C signals, the behavior of cy7c68 is quite reasonable. I would like to add that I am almost sure about the correctness of the hex data stored on eeprom.

tnx in advance