USB low-full-high speed peripherals Forum Discussions

 Hi 

My fx2lp is Slavefifo with fpga and sensor. 

Fx2lp out  garbage data (all 0)  when sensor's hsync is low. 

How am i supposed to handle these problem?

Can i use hsync instead for slwr? 

 Hi 

What happen slavefifo's flagd low and slwr low ?

Actually sensor's stream data flow cannot control. 

So what am i supposed to handle of this case?

Hi,

I'm working on a project, where we connected an Aptina optical sensor to the FX2 in GPIF-mode with external clock-source.

We connected

the LINE_VALID to RDY0,

the FRAME_VALID to RDY1

the pixel-clock to the IFCLK

and the pixel-data bus to D0-D7

pins of the FX2.

It works really well on the CY3681 developmen-kit with an rather old revision of the FX2 with 128-pins.

However on other board, with rather new FX2LP with 56-pins, the GPIF-wave once started will never get done, when I source the GPIF from the external clock-source (sensor generated pixel-clock).

When I experimentally switch the GPIF clock-source to internal clock, the wave will get done. In this case, the data are nonsense (because the GPIF is not synchronized to the pixel-clock) but I can see that my decision states (waiting for the start of the frame and start of the line) works...

On both boards I have connected the logic analyzer to the respective pins of the FX2 and can see that the signals from the sensor are the same. On the development-board, I see the states of the wave changing too. This I can't verify on the other board with the 56-pin version of FX2.

Can anybody please give me any hint, where else I should look?

Are there any specific differences between the different versions of the FX2, that might cause such a problem?

Any help is greatly appreciated.

 Hi

I'm not sure about these relation scheme. 

When i using slave fifo, fpga receive hsync from sensor. 

But i dont know how should i make slwr with hsync. 

Can i just use hsync for instance slwr?  

How am i make use hsync in slave fifo in FPGA

Could somebody help to me some advice?

 Hi

I willing to make reset signal to fpga from fx2lp. 

So i willing to use SYNCDELAY like this 

rst=0;

SYNCDELAY

SYNCDELAY

SYNCDELAY

rst=1;

Is that can possible way?

I am writing a program to communicate with a popular manufacturers lasers that have an FX2 board and ezusb.sys.

I have no problem sending, recieving data  with our 32 bit app under Win XP 32 bit via ezusb.sys

However the DeviceIOControl call to IOCTL_Ezusb_Get_Pipe_Info is returning strange results in Win7/Win8 64 bit.

The call says it suceeds but returns 120 bytes in Win64 instead of 96 bytes in Win XP.

The XP and Win 7 data is similar but differant. Its like structures and sizes of  elements have changed.

The structure says i have millions of endpoints instead of the expected 4.

Is it possible to communicate via ESUSB.sys on Win 64 machines to these lasers from 32 bit applications? Or can CyUsb communicate with an FX2 board?   

Couldnt find a forum for FX2 so if this is the wrong place, i apologize in advance.

 Hi

I use fx2lp 56pin and slave fifo mode. 

I have to make control like this. But it's not work way

TD_Init()

{

...

PORTACFG |=0x80;

...

OEA=0x01;

IOA=0x00;  //for led on

}

TD_Poll()

{

OEA=0x01;

IOA=0x00;

If(IOA & 0x02)

IOA=0x01;

Z

What is

What is wrong?

 Hi i want handle PORTA of fx2lp-56pin in slave fifo mode. 

More detail, i want make what PORTA.0 is output and PORTA.1 is input. 

But i don't know how am i supposed to make configuration in F/W. 

Also, could you please let me know what is different between OEA and IOA?