USB low-full-high speed peripherals Forum Discussions

Dear sir,

i ahve developed one code to download my firmware to cypress FX2LP. i am using the  cyusb's cyusb_control_transfer and i am catching the sent bytes and i get perfect match between the Bytes sent and the firmware file size

but sad part is my device doesnt get initialised

Note: Firmware is tested n works fine

i am pasting here my code please do rply and give suggestions.

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <unistd.h>
#include <sys/stat.h>
#include <fcntl.h>
#include "../../include/cyusb.h"



unsigned int DownloadFirmware();


int main (void)
{

unsigned int a = 0;

a = DownloadFirmware();

if(a == 1)
{
printf("\nsuccessful fd\n");
}

}


unsigned int DownloadFirmware()
{

        cyusb_handle *h;
        int size, r;
        int a, b, c, flag;
    int Sum = 0, Done = 0;
    const char *cbuf;
    const char *filename = "/home/usb/FPR/firmware/fw.bix";
    unsigned char *buf = NULL;
    unsigned char *ptr;
    unsigned char num_bytes = 0;
    unsigned short address = 0;
    unsigned char reset = 0;
    FILE *fp;   /* file pointer */
   



        struct libusb_device_descriptor desc;


        a = cyusb_open();

         if ( a < 0 ) {
              printf("Error opening library\n");
              return -1;
           }
        else if ( a == 0 ) {
                   printf("No device foundd\n");
           }

        h = cyusb_gethandle(0);
        b = cyusb_get_device_descriptor(h, &desc);

        if(b){
           printf("error getting device descriptor\n");
           return -2;
        }




        struct stat st;
        stat(filename, &st);
        size = st.st_size;
       
        printf("size of file = %d\n", size);   
   
            buf = (unsigned char*)malloc(size);       




     /* open file for read */
          if ((fp = fopen("/home/usb/FPR/firmware/fw.bix", "r"))==NULL){
              printf("Cannot open file \n");
        }     

        fread(buf, size, 1 ,fp);
   
        fclose(fp);
    if(buf)
    printf("file copied");

    int ChunkSize = 4000; // seem to sending 4000 but not 5000 at one time
    int BlockSize = size;
    int entry = 0;
    reset = 1;
    sleep(1);


    reset = 0;

        r = cyusb_control_transfer(h, 0x40, 0xA0, 0xE600, 0x00, &reset, 0x01, 1000);
        if (!r) {
           printf("Error in control_transfer\n");
           return r;
        }

    sleep(1);
    sleep(1);
   
    ptr = buf;
   
    while(!Done)
    {


            if(BlockSize < ChunkSize){
                                address += ChunkSize;
                   //             buf = buf+ChunkSize;
                             ptr = ptr + ChunkSize;
                                ChunkSize = BlockSize;
                                flag = 1;
                                }


     r = cyusb_control_transfer(h, 0x40, 0xA0, address, 0x00, ptr, ChunkSize, 30);

        printf("\nturn no. %d\n", r);
         if (!r) {
               printf("Error in control_transfer. . .\n");
               return r;
            }


                          //  buf = buf+ChunkSize;
                             ptr = ptr + ChunkSize;
                                BlockSize -= r;
                Sum += r;
                                if(Sum == size)
                                Done = 1;
    printf("\nsum =  %d\n", Sum);

    }


    sleep(1);


                reset = 1;
                        r = cyusb_control_transfer(h, 0x40, 0xA0, 0xE600, 0x00, &reset, 0x01, 1000);

                reset = 0;
                        r = cyusb_control_transfer(h, 0x40, 0xA0, 0xE600, 0x00, &reset, 0x01, 1000);
   
    sleep(2);



    if(Done == 1){
    return 1;
    free(buf);
    }
}

please help me i want to get out of this

Thanks in advance

Regards

Rohaan

I think I posted in the wrong forum previously, so I am going to repost my problem here. I have constructed an interface using an FPGA to drive the EP2FIFO. I am using the EP2FIFO FF as FLAGB, and the FPGA uses the flag to tell it when to stop sending data. Data is requested using EP8, and that part is working fine. However, EP2FIFO FF is going high after 64 bytes, which made me think the EP was working in low speed mode. However, I can see, using UCView, that the max packet size for the EP2 is 512 bytes, and the connection is high speed. I have to believe I m making an obvious mistake, but I do not see it. Here is my EPSetup:

void EPSetup(void)
{

//    HistctrlReset(1);



    REVCTL=0x1;     // Enhanced Packet Handling

    // set the slave FIFO interface to 48MHz
    IFCONFIG = 0x03;    // IFCLKSRC=0   , FIFOs executes on external clk source
                        // xMHz=0       , 48MHz internal clk rate
                        // IFCLKOE=0    , Don't drive IFCLK pin signal at 48MHz
                        // IFCLKPOL=0   , Don't invert IFCLK pin signal from internal clk
                        // ASYNC=0      , master samples asynchronous
                        // GSTATE=0     , Don't drive GPIF states out on PORTE[2:0], debug WF
                        // IFCFG[1:0]=11, FX2 in slave FIFO mode
    SYNCDELAY;                   

    // set up registers for EndPoint communication

    // Registers which require a synchronization delay, see section 15.14
    // FIFORESET        FIFOPINPOLAR
    // INPKTEND         OUTPKTEND
    // EPxBCH:L         REVCTL
    // GPIFTCB3         GPIFTCB2
    // GPIFTCB1         GPIFTCB0
    // EPxFIFOPFH:L     EPxAUTOINLENH:L
    // EPxFIFOCFG       EPxGPIFFLGSEL
    // PINFLAGSxx       EPxFIFOIRQ
    // EPxFIFOIE        GPIFIRQ
    // GPIFIE           GPIFADRH:L
    // UDMACRCH:L       EPxGPIFTRIG
    // GPIFTRIG
   
    // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
    //      ...these have been replaced by GPIFTC[B3:B0] registers
   
    // default: all endpoints have their VALID bit set
    // default: TYPE1 = 1 and TYPE0 = 0 --> BULK 
    // default: EP2 and EP4 DIR bits are 0 (OUT direction)
    // default: EP6 and EP8 DIR bits are 1 (IN direction)
    // default: EP2, EP4, EP6, and EP8 are double buffered

    // reset EP FIFOs
    // Reset all FIFOs
    SYNCDELAY;
    FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
    SYNCDELAY;                    // see TRM section 15.14

    EP8FIFOCFG=0x01;    //Use WORDWIDE
    SYNCDELAY;
    EP2FIFOCFG=0x05;    // use ZEROLENIN,WORDWIDE
    SYNCDELAY;

    FIFORESET = 0x02;             // reset, FIFO 2
    SYNCDELAY;                    //
    FIFORESET = 0x04;             // reset, FIFO 4
    SYNCDELAY;                    //
    FIFORESET = 0x06;             // reset, FIFO 6
    SYNCDELAY;                    //
    FIFORESET = 0x08;             // reset, FIFO 8
    SYNCDELAY;                    //
    FIFORESET = 0x00;             // deactivate NAK-ALL
    SYNCDELAY;


    SYNCDELAY;
    EP1OUTCFG=0xA0; //Bit 7 - Valid=1;
                    //Bit 6 - NC 0
                    //Bit [5..4] - TYPE=BULK(0x2);
                    //Bit 3 - Size=512(0);
                    //Bit 2 - 0
                    //Bit [1..0] - 0

    SYNCDELAY;                   
    EP1INCFG=0xA0;  //Bit 7 - Valid=1;
                    //Bit 6 - NC 0
                    //Bit [5..4] - TYPE=BULK(0x2);
                    //Bit 3 - Size=512(0);
                    //Bit 2 - 0
                    //Bit [1..0] - 0
    EP1OUTBC=0;
    SYNCDELAY;
       
    // Set up endpoints
    // Bit      Task
    //  7       VALID - turns on EP if 1
    //  6       DIR - 0=out;1=in
    //  5..4    TYPE - 0=invalid;1=ISO;2=bulk;3=interrupt      
    //  3       SIZE - 0=512;1=1024
    //  2       NC
    //  1..0    BUF - 0=quad;1=invalid;2=double;3=triple
    // EP1 is bidirectional


    SYNCDELAY;                   
    EP2CFG = 0xE2;  //Bit 7 - Valid=1;
                    //Bit 6 - DIR - 0=out;1=in
                    //Bit [5..4] - TYPE=BULK(0x2);
                    //Bit 3 - Size=512(0);
                    //Bit 2 - 0
                    //Bit [1..0] - BUF=DOUBLE(0x2)


    SYNCDELAY;                   
    EP8CFG = 0xA0;  //Bit 7 - Valid=1;
                    //Bit 6 - DIR=OUT(0);
                    //Bit [5..4] - TYPE=BULK(0x2);
                    //Bit 3 - Size=512(0);
                    //Bit 2 - 0
                    //Bit [1..0] - BUF=DOUBLE(0x2)
    SYNCDELAY;

    // Unused EPs still take up memory if they are not configured LAST.
    // FIFO memory is first come, first allocated.
    SYNCDELAY;                   
    EP4CFG = 0x2;   // disable; only double buffered

    SYNCDELAY;                    
    EP6CFG = 0x2;   // disable; only double buffered

    // Set up FIFO Operations
    // Bit      Task
    //  7       NC
    //  6       INEARLY - if 1, causes IN flags to appear one clock cycle earlier
    //  5       OUTEARLY  - if 1, causes OUT flags to appear one clock early
    //  4       AUTOOUT - if 1, data is auto-committed to USB (only used for OUT FIFO)
    //  3       AUTOIN  -   if 1, uses PKTLEN register
    //  2       ZEROLENIN - if 1, a PKTEND commits a zero-length packet
    //  1       NC
    //  0       WORDWIDE - if 1, data is 16 bits wide
//    EP8FIFOCFG=0x11;    //Use AUTOOUT,WORDWIDE

    EP8FIFOCFG=0x11;    //Use AUTOOUT,WORDWIDE
    SYNCDELAY;
    EP2FIFOCFG=0x0D;    // use AUTOIN,ZEROLENIN,WORDWIDE
    SYNCDELAY;

    // set up autoin length to be 512. if we are not high speed, we can only send
    // a maximum of 64 byte packets (see Descriptor). The AUTOINLEN must be the same
    // as the max packet in the descriptor.
    if(EZUSB_HIGHSPEED())
    {
        EP2AUTOINLENH=0x02;
        SYNCDELAY;
        EP2AUTOINLENL=0x00;
        SYNCDELAY;

    }
    else
    {
        EP2AUTOINLENH=0x00;
        SYNCDELAY;
        EP2AUTOINLENL=0x40;
        SYNCDELAY;
    }

    // EP2 FF = 0xC  EP8EF= 0xB
//    PINFLAGSAB=0xC8;   
PINFLAGSAB=0xCB;   
    SYNCDELAY;
//    PINFLAGSCD=0xFB;   
PINFLAGSCD=0xBB;  
    SYNCDELAY;
    PORTACFG |= 0x80;             // FLAGD, set alt. func. of PA7 pin
    SYNCDELAY;
    FIFOPINPOLAR=0x3; // we want all flags to be active high
    SYNCDELAY;


    // out endpoints do not come up armed
   // since the defaults are double buffered we must force 2 packets
    SYNCDELAY;                    //
    OUTPKTEND=0x88;
    SYNCDELAY;
    OUTPKTEND=0x88;



    // enable dual autopointer feature
    AUTOPTRSETUP |= 0x01;
   
}

 dear Sir /Miss

            i want to know how to download the firemare in  my application software.please give me some documentation about it . 

thanks!

aaron

 I am trying to get an FPGA interface working on a FX2LP. I have used the application note AN61345 Spartan 6 design, just changing the FPGA pins to match my own. If I use the USB control centre to send some bytes to the FX2LP it reports that it worked fine. However when I try to read them back it gives the following error.

BULK IN transfer failed with Error Code:997

Can someone tell me what this means? I am a bit surprised that the example design would not just work out of the box.

Thanks

Jon

.

I have a couple of questions about CY7C67300 after going through the data sheet.

1. I would like to use CY7C67300 in co-processor mode with HPI port interface. I need two Host ports and One device ports. I was planning to use port 1A as peripheral and ports 2A and 2B as Hosts. In this configuration what does the OTGID pin have to be tied to +3.3V or GND or left floating as I intend to use that port as a peripheral. Also is this configuration valid to use meaning port 1A as peripheral and 2A and 2B as hosts.

2. I came across some other application note from Cypress about HPI port and I am confused by one statement I found in it. It stated that BIOS will not configure port 1A or 2AS in co-processor mode. What does this imply? How else would I configure port 1A as peripheral and port 2A as host?

Thanks.