USB low-full-high speed peripherals Forum Discussions

i download CY3684Setup.exe .

my device pid is 8888 ,vid is 2222.so i change cyusbfx1_fx2lp/winlh-win7/x64/cyusbfx1_fx2lp.inf .

but it can not work.

where to download the latest 68013 win8 driver?

i download CY3684Setup.exe .

my device pid is 8888 ,vid is 2222.so i change cyusbfx1_fx2lp/winlh-win7/x64/cyusbfx1_fx2lp.inf .

but it can not work.

where to download the latest 68013 win8 driver?

I'm working on my own streaming application (we're collecting high speed serial bitstream, converting it to parallel, and shipping it up USB).  We have an FPGA doing the serial->parallel conversion,  doing its own internal FIFOing, and feeding the FX2 slave interface as a master. (8 bit bus, synchronous--i think--, 40Mhz IFC clock sourced by the FPGA, SLWR pulsed when there's data to feed, etc).

When I use the cyconsole, my device shows up, reports my in end points, and is able to read 512 bytes when I do a bulk in.

I can write an application using CYApi to repeatedly do XferData() 512 bytes at a time.   My data stream is fast enough, however, that the FX2 fifo gets full and I'm forced to drop data. (I manage about 4MB/s)

So, I switched to overlapped IO (BeginXfer, WaitForXfer, FinishXfer) again with 512 bytes, and I can manage about 8MB/s, but I'm still being forced to drop data (we generate about 10MB/s).

So I started using large transfers (32KB, for example), at this point FX2/FPGA operate for a short time, and then would fall over and enter a stall state.  I don't know if this is normal or not.

I suspect this is when the FX2 FIFO becomes empty (which only happens when I'm transferring  enough data out of the system that I can drain the FX2 FIFO and the 4KB fifo on the FPGA) and I'm not doing something right at that point.  

TL;DR:   what can cause a bulk in endpoint in AUTOIN Slave FIFO mode to enter stall state?   I would have expected the endpont to NAK until data became ready, not stall.  (full disclosure, I haven't examined the USB bus, but when I get the URB stat after the pipe locks up it says stalled)

I can post the entirity of my slave.c and my win32 C simple streaming source code on monday when I get into the office.

 I'm implementing some very simple class specific (USBTMC class) setup requests on the FX2LP. I get a SUDAV interrupt, check for the  class request flag in SUDAV[0], and if it's there I decode the request and send back a one or two byte payload to EP0 depending on the request. Very simple and straightforward and 80% of the time this works fine.

HOWEVER, 20% of the time there is a 1-10 second delay between the setup transaction and the receipt of the SUDAV interrupt. I can see the setup transaction on my protocol analyzer. It completes, including the ACK, in a couple of usec and occurs exactly after I send the request from the host. But the corresponding  interrupt (which I detect by toggling an output bit in the interrupt routine),  which is supposed to happen right after the ACK, doesn't occur for multiple seconds (variable between 1-10) afterword. 

Does anyone have any idea what could be causing this? The time scale of the delay, multiple seconds, is kind of baffling. what could be holding off the interrupt that long? I've enabled the SUTOK interrupt and it's delayed as well.

Thanks in advance,

Andrew

 Hello, everyone, i am using the chip cy7c68013a to access an usb  port.

The schematic is as belows in the attachment:

and now i plug a usb into the pc, the pc find new device in the "device manage" , but could nor recognize it.

and i have installed the driver for this chip, but the pc still could not find the device,

it have measure the voltage ,and i am sure that the reset/wake up is high and the wake up is low

How could i solve the problem, could you give me some help？

Thank you

 Hello,

I have been working on the project provided with AN61345 application note (http://www.cypress.com/?rID=43046). The VHDL files and application notes are provided with the project.I am trying to create a top level and test bench file for the StreamIN, StreamOUT and Loopback.

The application note shows the hardware connection in figure 10 which is shown below. 

I do not understand the use of PA1, PC0, PC1 signals?

On the documentation it says PC0 is used for synchronoizing the data trasnfers between the FPGA and FX2LP and PC1 is used to know the readliness of FPGA to supply the Slave FIFO interface clock (IFCLK). I had a look in Technical Ref. manual but it only talks about the pin connects of these 3 signals.

The VHDL code provided for StreamIN, StreamOUT and LoopBack does not mention PC0, PC1 and PA1 anywhere.

How and Where I should connect the PC0, PC1 and PA1 on the VHDL project document (Top Level & Test Bench)?

Last summer, after hearing for months that Cypress was going to have an Eclipse based development tool for the FX2LP, I downloaded version 0.0.0 of the "Cypress EZ-USB Suite". The software was incredibly buggy, and obviously only paid lip-service to the FX2LP, but I managed to get it working and do some useful development with it.

Checking back now, I find no mention of these tools for the FX2LP, but only the Cypress EZ-USB FX3 software,

Does the new package include support for the FX2LP?

Was there ever an update to the 0.0.0 release of the EZ-USB Suite that did support the FX2LP? Is there a link to it somewhere? 

 Hi 

i'm using FX2LP in ISO & GPIF

i config EP2 as ISO OUT , AUTOOUT = 1; EP6 as ISO IN, AUTOIN = 1;

i want to test is there any packet missing during ISO IN/OUT and GPIF FIFO read/write , but the ez-usb cpu can't cap isoerr interrupt in this configuration, and the host aways says the iso transfer is successful.

what do i need to do ?

thanks !

Hi everybody,

I'm getting a strange error with CY7C68013A.

An image sensor is filling the endpoint FIFOs in AutoIN mode and data is sent through an Isochronous pipe. If I send 1pkt/uFrame, data are correctly received by the host, if I send 2 or 3 iso pkts/uFrame, I get an error from the host controller (E0000B00:Iso Request Failed and every packet has status E0000011: XACT error).

FIFO is configured with AUTOIN and ZEROLENIN.

Here is the code:

             case Alt3_IsocIN:                 // Only using endpoint 2, zero the valid bit on all others                 EP2CFG = 0xD8;  // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x                 SYNCDELAY;                  EP2FIFOCFG = 0x0d;                 SYNCDELAY;                                  EP1OUTCFG = EP1INCFG = EP4CFG = EP6CFG = EP8CFG = 0x00;                 SYNCDELAY;                      // Clear out any committed packets                 FIFORESET = 0x80;                 SYNCDELAY;                 FIFORESET = 0x02;                 SYNCDELAY;                 FIFORESET = 0x00;                 SYNCDELAY;                      // This register sets the number of Isoc packets to send per                 // uFrame.  This register is only valid in high speed.                 EP2ISOINPKTS = 0x03; // with EP2ISOINPKTS = 0x01 WORKS!!!

break;

and the descriptor:

;; Isoc OUT Endpoint Descriptor       db   DSCR_ENDPNT_LEN   ;; Descriptor length       db   DSCR_ENDPNT       ;; Descriptor type       db   02H               ;; Endpoint 2 and direction OUT       db   ET_ISO            ;; Endpoint type       db   00H               ;; Maximun packet size (LSB)       db   14H               ;; Max packect size (MSB) 10100b 3x1024 byte packets/uFrame       db   01H               ;; Polling interval

I tried to manual flush the FIFO and in this case I correctly receive 3 pkts/uFrame!!!

Unfortunately I've no hardware protocol analyzer, so I cannot give deeper info about the isochronous transaction!

Thank you in advance!