USB low-full-high speed peripherals Forum Discussions
I have an application that requires 640x480 video at 30 FPS (such as from an OV 5640), as well as audio in and out to be transmitted over USB 2.0 using UVC and UAC. Is the FX2LP capable of doing this? If so, will I need to employ any sort of video and/or audio compression? If the FX2LP can not handle this, is there an alternative device that can?
Thanks...
Brian
Show LessHi,
I'm using Fx3 to stream UVC data successfully. I'm basing my program on Cx3UvcOV5640 sample.
In parallel I'm sending (very small and rare) control packets to the device on the EP0.
Sending these control packets sometimes sporadically cause the image to become vertically unsynchronized.
Sending a few more of the control packets sometimes sporadically restores the image to the normal state.
Digging a little deeper, I see that the function
CyU3PDmaMultiChannelCommitBuffer
returns 71 (CY_U3P_ERROR_INVALID_SEQUENCE)
around the time where the issues begin.
Do you have an idea as to what might have gone wrong with the DMA, and how I should handle it ?
Thanks,
Roman
Show LessI need driver for Linux (Raspberry PI) for CY7C68013A.
Is this driver available and can install in raspberry(rasbain)?
EZ-USB FX3 SDK v1.3.3 for Linux maybe can slove it,but i have no idea to install it in raspberry pi.
But how do i getting start it. Entire tar.gz(422MB) put into raspberry pi?
any one can give me some suggestion or user guide ?
Thanks.
In pi i enter lsusb can see ID 52cb:52cb . Is it OK?
pi@raspberrypi:~ $ lsusb
Bus 001 Device 011: ID 046d:c52b Logitech, Inc. Unifying Receiver
Bus 001 Device 010: ID 04d9:1702 Holtek Semiconductor, Inc.
Bus 001 Device 009: ID 1a40:0101 Terminus Technology Inc. 4-Port HUB
Bus 001 Device 012: ID 52cb:52cb
Bus 001 Device 003: ID 0424:ec00 Standard Microsystems Corp. SMSC9512/9514 Fast Ethernet Adapter
Bus 001 Device 002: ID 0424:9514 Standard Microsystems Corp.
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
I want to use cypress fx2 to emulate epp parallel port can any one help to develop code for fx2 .or any application note regarding epp emulation on fx2
Show LessHi,
I have a question When is try to build the firmwarer for FX2LP using keil uVision2.
The build result is shown attached pic.
I can’t find the exit-code =4
also, I don’t know what is means
could you give me solve or advice about this problem.
My dev system base on windows10, and I try also windows7 dev system too. But it’s result same.
Show LessHello
i am new at cypress. i used avr, nxp, stm32 but i havent used cypress devices before. when i saw psoc arm and psoc creator i am amazed and i liked it.
Now i see lots of usb devices on cypress.
i want to send data from psoc arm to usb 2.0 / and from computer i want to send some data to psoc 5lp. there are lots of usb modules but i cant select them clearly. For example i measured adc and i want to send it to computer. but i dont want to use usb/uart converter. i need fast communication. usb2.0 12mbit/sec or 480mbit/sec.
Can you help me which one must i use?
thanks in advance
Show LessHi!
I'm new with CYUSB and met some problems. I have made my own PCB with Altera FPGA and CY7C68013A. And I have made a mistake that I set the IFCLK pin in FPGA side as an input only pin so I have to use 68013A's internal clk.Is my understanding right that I can use it that way in synchronous slave FIFO?
I have test my code, and found when I assert SLOE and SLRD, FD[7:0] can set the first data correctly but it seems that the FIFOptr never change, data did not change and empty flag remain high.then I try it in writing, than I found the same problem ,Ican see the FPGA program function well that the FD[7:0] repeatly raising from 0 to 256, SLWR low and IFCLK in a sin curve but empty flag still low.
I also tried Asynchronous mode and met the same problem.
I have upload my code. It wouldn't be more thanksful from me that anyone could help me to solve that problems.
Show LessHi there,
I'm trying to establish a synchronous Slave FIFO read between the FX2 and an FPGA.
The FPGA is providing the interface clock (20MHz) and runs a state machine that toggles the SLRD and SLOE lines according to figure 9-17 in the Technical Reference Manual.
If I now send data over USB to EP2 I expect the data to be driven out on the FD (byte wide) lines. I get the right amount of rising clock edges according to how many bytes I have sent to EP2 until the empty flags gets deasserted. However, the FD lines seem to be stuck on the first byte, or are alternating between the first two bytes for the whole transmission. I attached a picture of the logic analyzer software.
Has anyone seen something like this before? Any solutions.
Show Lesshi, i want to program FX2LP's Ram in a C++ application.(precisely what Control Center do when click ProgramFX2=>RAM). but the function LoadExternalRam (in C# source of control center) is not available in CYAPI. what i should to Do?
thanks
Show Less