USB low-full-high speed peripherals Forum Discussions
I have designed a PCB for Cy7C65211 IC. In datasheet the default VID & PID is given and after connecting it to the PC the system throws error as "Device Descriptor Request failed" in the device manager. I tried to change the *.inf file, but need further assistance.
Show LessHi,
I am searching for USB to UART/SPI/I2C converter, where i need UART and SPI at the same time.
I have found CY7C65215 have 2 different channels.
My Query is, shall I use one channel for UART, GPIOs & Another channel for SPI, GPIO's.
SCB0 as MODE 2 and SCB1 as MODE 4 at the same time?
Thaks & Regards
Jones (Jones.rajasekar@light.co)
Show LessI want to use external SRAM for cy7c68013a-128pin(fx2).
Because firmware larger than the internal memory of EZ-USB.
How to connect PSEN, RD, WR, CS, OE, EA. and build option.
( I used SRAM CY7C199D-10ZXI.)
my build option
.\hex2bix -i -e -m 0x2000 -f 0xC2 -o filename.iic filename.hex
what is probrom?
Show LessHi all:
According to the FX2LP's datasheet, the SLRD and SLWR setup and hold times are virtually impossible to meet at 48 MHz: the setup time is listed as 18.7 ns with a minimum hold time of 0 ns for SLRD, and 18.1 ns with a minimum hold time of 0 ns for SLWR. With a 20.83 ns clock, this means that the data only has 2.13 and 2.73 ns to change, over all process/voltages/temperature. For virtually any FPGA design this is essentially impossible to meet.
What I don't understand is that Cypress has an FPGA FX2 slave FIFO design published at AN61345:
http://www.cypress.com/?rID=43046
and that design explicitly does *not* meet the timing requirements in the datasheet. Not even particularly close: the timign report loopback/Loopback_verilog/fpga_master.twr gives:
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
faddr<1> | 7.873(R)|clk_BUFGP | 0.000|
fdata<0> | 9.839(R)|clk_BUFGP | 0.000|
fdata<1> | 10.479(R)|clk_BUFGP | 0.000|
fdata<2> | 9.943(R)|clk_BUFGP | 0.000|
fdata<3> | 10.487(R)|clk_BUFGP | 0.000|
fdata<4> | 10.263(R)|clk_BUFGP | 0.000|
fdata<5> | 10.275(R)|clk_BUFGP | 0.000|
fdata<6> | 10.765(R)|clk_BUFGP | 0.000|
fdata<7> | 8.748(R)|clk_BUFGP | 0.000|
gstate<0> | 8.812(R)|clk_BUFGP | 0.000|
gstate<1> | 8.851(R)|clk_BUFGP | 0.000|
gstate<2> | 7.434(R)|clk_BUFGP | 0.000|
sloe | 8.575(R)|clk_BUFGP | 0.000|
slrd | 7.768(R)|clk_BUFGP | 0.000|
slwr | 8.581(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
You can see here that SLRD and SLWR have a clock-to-out time of ~8 ns, which implies, with a 20.83 ns IFCLK (which the firmware included with AN61345 uses) a setup time of ~13 ns, which is about 5ns *shorter* than the time specified in the FX2LP datasheet.
Does anyone have any idea what the real setup time requirements are for SLRD/SLWR for the FX2LP, or is it just impossible to run IFCLK at 48 MHz over all operating conditions?
Show LessWe have confirmation about CY7C65213-32LTXI.
I am using "CYUSB 232 USB-UART LP REFERENCE DESIGN KIT" to ”comfirm for the operation.
BM option does not exist in USB - UART driver detailed setting.
Is it impossible to set the waiting time?
We would like to consider the BM mode in order to prevent the communication speed from becoming slow.
Regards,
Masashi
Show LessHello,
fx2lp clock is having external clock source as 24MHz,(not using crystal oscillator).but if i set CPUCS = 0x02; that is 12MHz,
if i do this,Is fx2lp clock reduced to 12MHz even its supplied with 24MHz?
or
its only effect on SYNCDELAY?
let me know.
regards,
geetha.
Show LessHello
I wonder if its is possible to make the CY7C68013A-56 load the EEPROM content from a microsontroller?
More explanation, the board loads the content from 24C256 via SDA SCL, is it possible to make it read that content from a microcontroller?
Thanks
Show LessHello,
I am using usblyzer,i am able to capture the data,but every time data transfer from fx2lp to host is fixed to 4 bytes only(raw data).how to solve this?
i have attached the screenshot of usblyzer.please help me.
regards,
geethanjali
Show LessHi all,
I am encountering a problem with CY7C68013A.
Using the cyusb3.inf from driver for win7 (I am using win10) and adding custom PID/VID/Desc in .inf file, the device can be correctly recognized by windows device manager, Cypress control center and USB console. (The EEPROM is not connected by far.)
But, when I use control center to program the firmware (from bulkloop example) file .hex/.iic to RAM/EEPROM, the programming process looks fine, but after this point, the device can be recognized by device manager with new name, but can NOT be recognized by control center or USB console. In fact, control center and USB console freeze without any response. (or it takes more than 1 min to launch, and showing no device.)
And if I reset the 68013, control center and USB console can recover immediately, and recognize the device with the default PID/VID and device name.
What causes this problem?
Thanks and any help will be appreciated.
Best,
Zheng
Show Less