USB low-full-high speed peripherals Forum Discussions
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We have a scenario in which we are developing a board application (including two PSoCs) for an international customer. Our present Silicon Laboratories USB bridge chip requires SiLabs drivers to be installed on the user's machine. The IT departments of many customers (including this company) prohibit the loading of non-standard external drivers in their employees machines. From the CY7C65215 datasheet it appears that the standard Windows driver will/may be used if all we are doing is UART-to-USB traffic. Nothing special. However, the CYUSBS236 development kit is showing no way around installation and use of the Cypress driver.
We found we could force Windows to load the standard Microsoft driver by modifying the VID/PID, Tests with a terminal emulator showed the USB bridge to be functioning. However, after changing the VID/PID we can no longer change it back to the Cypress default because we can't list it in the configuration utility anymore. The chip is functional, but bricked from a configuration standpoint. Is there a way to unbrick it?
This can't be this difficult. How do we force the use of the standard Windows driver which we believe is USBSER.SYS?
Thanks.
Show LessHi all,
I am trying to use isoc transfer in CY7C68013. I have 2 interface settings: alt-0 for bulk transfer and alt-1 for isoc transfer.
After device plugged in PC, the default setting alt-0 works. Then I select alt-1 and it also works. But when I select altl-0 again, the transfer failed.
I tested this using CYStreamer and ControlCenter. I also used Bus hound to capture all the transfer, as following figure.
I can not figure out why it cannot get the endpoint back to alt-1 setting correctly. What may be the reason?
I am using the following two functions (set_ep2_isoc_mode and set_ep2_bulk_mode) to set the interface in DR_SetInterface.
Here is the code snippet.
BOOL DR_SetInterface(void)
{
AlternateSetting = SETUPDAT[2];
SYNCDELAY;
switch(AlternateSetting)
{
case alt0_bulk_in:
set_ep2_bulk_mode();
break;
case alt1_isoc_in:
set_ep2_isoc_mode();
break;
}
return(TRUE);
}
// for alt-setting-0
void set_ep2_bulk_mode(void)
{
// only use EP-1 out and EP-2 in, disable EP1_IN and EP4.6.8.
EP1INCFG &= 0x7F;
SYNCDELAY;
EP4CFG &= 0x7F; // EP4 not valid
SYNCDELAY;
EP6CFG &= 0x7F; // EP6 not valid
SYNCDELAY;
EP8CFG &= 0x7F; // EP8 not valid
SYNCDELAY;
// configure EP-1 bulk-out mode
EP1OUTCFG = 0xA0; // valid, bulk
SYNCDELAY;
EP1OUTBC = 0x40; // arm the EP1 OUT endpoint by writing to the byte count
SYNCDELAY;
// configure EP-2 as bulk-IN
EP2CFG = 0xE8; // BULK-IN, 0xE0: 512*4 bufferred, 0xE8: 1K*4 bufferred
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80; // reset all FIFOs
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x84;
SYNCDELAY;
FIFORESET = 0x86;
SYNCDELAY;
FIFORESET = 0x88;
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
EP2FIFOCFG = 0x0C; // b3:AUTOIN=1, b2:ZEROLEN=1, b0:WORDWIDE=0
SYNCDELAY;
EP2AUTOINLENH = 0x02; // Auto-commit 0x0200 = 512B, 0x0400=1KB
SYNCDELAY;
EP2AUTOINLENL = 0x00;
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
return;
}
// for alt-setting-1
void set_ep2_isoc_mode(void)
{
// only use EP-1 out and EP-2 in, disable EP1_IN and EP4.6.8.
EP1INCFG &= 0x7F;
SYNCDELAY;
EP4CFG &= 0x7F; // EP4 not valid
SYNCDELAY;
EP6CFG &= 0x7F; // EP6 not valid
SYNCDELAY;
EP8CFG &= 0x7F; // EP8 not valid
SYNCDELAY;
// configure EP-1 bulk-out mode
EP1OUTCFG = 0xA0; // valid, bulk
SYNCDELAY;
EP1OUTBC = 0x40; // arm the EP1 OUT endpoint by writing to the byte count
SYNCDELAY;
// configure EP-2 as isoc-IN
EP2CFG = 0xD8; // ISOC-IN, SIZE=1024, BUF=4x
SYNCDELAY;
FIFORESET = 0x80; // reset all FIFOs
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x84;
SYNCDELAY;
FIFORESET = 0x86;
SYNCDELAY;
FIFORESET = 0x88;
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
EP2FIFOCFG = 0x0C; // b3:AUTOIN=1, b2:ZEROLEN=1, b0:WORDWIDE=0
SYNCDELAY;
EP2AUTOINLENH = 0x04; // Auto-commit
SYNCDELAY;
EP2AUTOINLENL = 0x00;
SYNCDELAY;
EP2ISOINPKTS = 0x83; //b7 = AADJ
SYNCDELAY;
return;
}
Any help will be appreciated.
Thanks,
Zheng
Show LessWe are using CYUSB3065-BZXC. In our system, GPIO 17-GPIO25 are used as output. Our problem is: " if " io_cfg.gpioSimpleEn[0] = 0x3FE0000;, etc. using GPIO17-25",then "CyU3PDeviceConfigureIOMatrix (&io_cfg)" return fail;and if"io_cfg.gpioSimpleEn[0] = 0x3E00000”; Then "CyU3PDeviceConfigureIOMatrix (&io_cfg)" return success; and GPIO21-25 are OK。How to use GPIO 17-20 correctly?
Show LessHello,
what is the minimum initial ifclk clock cycles in order to sample data lines in fx2lp?
after how many clcok cycles from the master,fx2lp is going to sample data lines in slavefifo interface?
regards,
geetha.
Show LessI have to migrate some c# hostapplications, depending on AN21XX based controller, which are using EZBUSB.Sys driver to WIN10 64bit.
Can you please give me some hints for the recommended method?
Is it possible to use the Cypress Suite USB 3.4.7 ?
Show LessHi,Sir!
My code is bigger than 16K bytes, I select 64K bytes I2C Eprom and also attach one 64K bytes parallel SRAM as external Code(EA = 0) . the following description is from TRM:
The Main RAM is accessible both as program and data memory, just as in the 56- and 100-pin
FX2.
To avoid conflict with the Main RAM, the pins which control access to off-chip memory (the RD,
WR, CS, OE, and PSEN pins) are inactive whenever the FX2 accesses addresses 0x0000-
0x1FFF. This allows a 64K memory chip (data and/or program) to be added without requiring additional
external logic to inhibit access to the lower 8K of that chip. Note that the PSEN and RD signals
are available on separate pins, so the program and data spaces outside the FX2 are not
combined as they are inside the FX2.
When code in the range 0x0000-0x1FFF is fetched from the on-chip RAM, the PSEN pin is not
asserted; when code is fetched from program memory in the range 0x2000-0xFFFF, the PSEN pin
is asserted.
It seems that although we can program 64K I2C E2prom by Console app, it said only 16K bytes can be loaded into internal low 16K byte by hardware bootloader , I like C0 or C2 mode, because it is very easy to debug or deliver code.
Does the C0 or C2 mode support more than 16K bytes code?
Show LessHi all,
I am using CY7C68013 to design a USB2.0 device. I am confused by the buffer settings in the firmware.
In my firmware, I use EP2 in slave-FIFO bulk-IN mode.
My questions are:
1. The maxPacketSize (payload) for bulk EP2 can only be 512B, right? If so:
2. When setting EP2CFG, can I use the buffer size of 1024 for bulk EP2? Or I can only use 512 because maxPacketSize=512?
3. When auto-IN mode is used, can I set the EP2AUTOINLEN as 1024 for bulk EP2? Or I can only use 512 because maxPacketSize=512?
From the endpoint configuration-12, it seems that EP buffer can be set as 1024x4, but I am not sure if this only valid for iso mode. From the technical reference manual and datasheet, I didn't find clear presentation about this.
I set the EP-buffer=512, autoLength=512, the device works. But when multiple devices work simultaneously, some data will lost. So, I am thinking to make full use of the FIFO buffer, like configuration-12, in Bulk EP mode.
Thanks,
Zheng
Show LessDear Madam/Sir:
We attached BDAdriver_interrupt_working_current, but not sure how to compile it, Would you please kindly answer these question:
1、what is the compile enviorment ? linux ?windows?
2、If it is linux enviorment, the Makefile can not work.
3、If it is windows enviorment, what is the IDE should be used to compile it?
Beside, would you please kindly give us a BDA driver guide for our ATSC tuner dongle?
Sincerely Thanks
Show Less