I want to get more information about the CY7C68023 controller:
Would like to get as much information about this development board.
Thank you.Show Less
We have been performing some tests under Linux with the CY7C65215A running in i2c master mode.
When no receiver is present with the transmitted address or the receiving device is busy and unable to respond so a NACK occurs that the CY7C65215A appears to be holding the SCL line low until a USB timeout occurs.
Would you please advise how to overcome this issue? We are running under Linux.
Would you please advise if there is a Linux solution for the CY7C65215A Errata 5 - I2C Reads are slower when USB-Serial is configured as I2C Master?
The workaround provided lists a windows solution only.
I would like clarification on certain comments made in this post:
#1: Are pullups/pulldowns REQUIRED on the JTAG pins, or just SUGGESTED? If required, please confirm which pins get pullups/pulldowns.
#2: @YatheeshD_36 makes the comment: "Once SCB 1 is configured as JTAG the other interface in CY7C65215 cannot be used." This is NOT my understanding. I thought the restriction was that SCB 0 and SCB 1 could not be used concurrently. Please clarify, as this will severely affect my design.
#3: (unrelated to the referenced post): In the datasheet, revision M (https://www.cypress.com/file/129956/download) table 17 shows that SCB1 Mode 7 (JTAG) has TDO as pin 5, and TDI as pin 6. In prior versions, these two were swapped. Please also confirm that revision M is correct.
Thank you.Show Less
I have a question about the ATA standards supported by theI have a question about CY7C68300C-56LTXC
I use the IF below. Is there a compatibility issue?
-ATAPI command: Compliant with SFF-8020 Rev2.6 and SFF-8090 Rev0.99 specifications
・ Transfer mode:
PIO mode 0,1,2,3,4
Single Word mode 0,1,2
Multi Word mode 0,1,2
I checked the data sheet, but some modes are not supported.
Should we determine in the system that an unsupported mode is needed?
CY7C68300C-56LTXC The following signals are not supported.
Does CY7C68300C-56LTXC support only one ATA device?
Is the above signal unnecessary if there is only one ATA device?
Does the CY7C65215A Linux API provide a method for i2c stuck bus recovery? i.e. if a device connected to the master is holding the SDA line low can the CY7C65215A clock out the slave device so that it releases SDA?
What is the power consumption of the FX2LP18 when held in reset for both the three different supply inputs? I am working on a very power sensitive design and the USB will only be needed when powered externally. When in battery mode, I want to minimize the power consumption as much as possible by holding the part in reset (or even adding a power switch if necessary). The datasheet shows Isusp current, but it is not clear which power rail that is referring to. Also, it's not necessarily the same as when the part is in reset.Show Less
We are using a third-party configurable HID board which uses the CY7C64215. I would like to integrate this function onto our own board, which will need support for at least 5 years. Is the CY7C64215 still a good choice for this, or should we use a newer IC?
Our application is only 8 buttons and 2 analog inputs which need to be used as USB HID devices.
Use CY7C65213A to replace FTDI FT232, together with a SP3485 , found in the debugging process with CY7C65213A pin13 and 14to control SP485 DIR, the chip can not achieve this function, check the chip manual, discovered that the default state for the chip is not used to control SP485, manual suggest to manually configure, but we are under Linux debugging to provide development kit, not success.Show Less