Anonymous
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Feb 16, 2009
09:14 PM
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Feb 16, 2009
09:14 PM
I am designing a product around an Atmel micro and a CY6936 WLUSB module. This module is complete and sold by Unigen (and others) so I'm not working with the chip itself - just using the SPI interface to it.
I believe I can set a bunch of registers to make this work - the manual says that transaction mode is autonomous. However tech support at Cypress has been a bit lacking - seeming to think that this is going to be very difficult to do. I'm pressing on anyway.
I believe I have all the registers defined in what they need to be but am a bit confused by a few points. First register TX_IRQ_Status bit 1 [TXC IRQ] and 0 [TXE IRQ]. The wording is, well shall we say it leaves a bit of uncertainty. One would think that you could read this and if, when read, TXC were set then TXE would be valid - since indeed the transaction is done! However there is something about if it reads TXC=1 TXE=0 that you then have to read it again! I'm not exactly sure why. I believe it's saying that one can get a completed transaction and have an error in the transmission but not have the TXE set! If so then what use is it??
Essentially all I am trying to do is to use it in transaction mode (by the way nowhere in the manual does it say specifically HOW to get it INTO transaction mode except a veiled statement for bit 7 of XACT_Cfg), load the tx buffer, send 3 bytes, receive an ACK (which is automatic in transaction mode) and just confirm that I have received an ACK - then repeat 100mS later. Simple. Is there a better way to detect that a packet was successfully sent?
I believe I can set a bunch of registers to make this work - the manual says that transaction mode is autonomous. However tech support at Cypress has been a bit lacking - seeming to think that this is going to be very difficult to do. I'm pressing on anyway.
I believe I have all the registers defined in what they need to be but am a bit confused by a few points. First register TX_IRQ_Status bit 1 [TXC IRQ] and 0 [TXE IRQ]. The wording is, well shall we say it leaves a bit of uncertainty. One would think that you could read this and if, when read, TXC were set then TXE would be valid - since indeed the transaction is done! However there is something about if it reads TXC=1 TXE=0 that you then have to read it again! I'm not exactly sure why. I believe it's saying that one can get a completed transaction and have an error in the transmission but not have the TXE set! If so then what use is it??
Essentially all I am trying to do is to use it in transaction mode (by the way nowhere in the manual does it say specifically HOW to get it INTO transaction mode except a veiled statement for bit 7 of XACT_Cfg), load the tx buffer, send 3 bytes, receive an ACK (which is automatic in transaction mode) and just confirm that I have received an ACK - then repeat 100mS later. Simple. Is there a better way to detect that a packet was successfully sent?
1 Reply
Anonymous
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Jul 28, 2013
12:27 AM
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Jul 28, 2013
12:27 AM
Please refer to WUSB-LP for more detailed explanation of the product.
The TRM can be found @ http://www.cypress.com/?id=19&rtID=117