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USB Low-Full-High Speed Peripherals

New Contributor

Hello,I have some problems about CY7C68013A.I have a project that must connect to FPGA and Linux with cy7c68013a.It was very successful when it came out from Linux,but have problem when back.More pages related to LINUX have been marked as obsoleted.I don't know how to let it actively receiving signals from FPGA. Which part I need to modify , I only hope that it can send and receive correctly.

On the FPGA, I use the AN61345 example.On Linux, I use libusb and old FX2LP kit.(maybe?the page is disappear

Is there any expert who can help?

I am not too familiar with LINUX.

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Employee

Hi Huang,

I understand that you have problem when you try to transfer data to host. However, you are not able to give more detailed information which could help us to understand more.

You have mentioned that you use BeagleBone to act as host. I have no idea about this board. But you mentioned that you have checked your design with PC to find that bi-direction data transferring works well. I presume that could help us the locate the problem. Maybe you make something wrong on host side.


Hope it will help.

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Employee

Hi ,

Could you please explain your question? I notice your description but could not understand what problem you are facing now.

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New Contributor

My question is that I can't use CY7C68013A to pass signals from FPGA to LINUX. But from LINUX to FPGA is ok.

My FPGA code is from a example of AN61345, linux c program is from cyusb_linux_1.0.4 simple.

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Employee

You still not make a clear description. AN61345 is the application note which shows the FX2LP slave FIFO.

What do you mean by saying "I can't use CY7C68013A to pass signals from FPGA to LINUX"? Do you mean that you could transfer data from host(PC) to FPGA but failed to transfer data from FPGA to host(PC)?

Do you make a correct hardwre design? Could you confirm that you make a correct firmware design?

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New Contributor

yes.

I said AN61345 because my firmware and verilog use AN61345's source code in this page.(.zip)

http://www.cypress.com/documentation/application-notes/an61345-designing-ez-usb-fx2lp-slave-fifo-int...

I have not made any changes.

I could transfer data from host to FPGA.It's verified by a logic analyzer.

But there is always a problem  from FPGA to host.

I connected to PC and used Cypress>CyConsole can see it's okay to translate in two way.

I am not sure if the problem is with my device or source code.

My Linux device is BeagleBone Black.Is it probably the problem?

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Employee

Hi Huang,

I understand that you have problem when you try to transfer data to host. However, you are not able to give more detailed information which could help us to understand more.

You have mentioned that you use BeagleBone to act as host. I have no idea about this board. But you mentioned that you have checked your design with PC to find that bi-direction data transferring works well. I presume that could help us the locate the problem. Maybe you make something wrong on host side.


Hope it will help.

View solution in original post

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New Contributor

I think it could be.

On windows, CyConsole is transfer actively when I click the buttom.But on Linux, Cyusb is passive.It just only few command can be called.

I think the problem maybe on the buffer?FPGA always give the same signal,the buffer could be full?

I don't know if it could be interrupt and show when the buffer wasn't full.

Have any better method to write the code?

The attachment is the two method I found.

I think I'm really poor at this, which part I can start from will be easIier?

yyca​ Thanks for your patience. My English is not fluent.Broken articles should be difficult to read.

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