Some register questions about cy7c68013A speed

[Anonymous]

        I ultize cy7c68013a chip to fullfil a bulk transfer.I have configured EP2 as OUT endpoint,bulk,quad buffer(4*);ep6 as IN endpoint,bulk,quad buffer(4*),but now I have confronted a data losing problem.I want to know what registers are related to the transfer speed(or packetsize).   
   
Otherwise,I have read some references and was confused by following packet-related concepts:maxPacketSize,EPxBCL/H,AUTO2/4/6/8INLENGTHL/H.   
   
Thank you for your reply!   

[Anonymous]

        What is the speed you are obtaining? What is the dataloss problem you are talking about, can you please explain?   
For bulk using quad buffered 1024 packet size should give you maximum speed. Here what you have to know is that the device is not the bottleneck when it comes to speed. It is the OS.   

[Anonymous]

        Max Packet Size is a descriptor value that is used by the USB Host Controller to understand how it should packetize large amounts of data. The value only matters to the computer-side of the FX2, at the other end of the USB cord. The FX2 itself doesn't really care too much about the value in the descriptor.   
   
EPxBCL/H are registers that are used by 8051 firmware to either interrogate how much data arrived from the host, or to indicate to the host how much data has been provided in the endpoint buffer. These registers are used when you're internally reading or writing to the endpoint buffers.   
   
Auto in length registers allow the FX2 to automatically packetize large amounts of data from the device-side of the FX2. It only matters if you have an external device writing bytes into the FX2's Slave FIFOs or GPIF.   
   
I highly recommend finding the FX2LP's Technical Reference Manual and reading chapters 8 (Access to Endpoint Buffers) and 9 (Slave FIFOs) - they will explain what all of those registers are for.   

[Anonymous]

        Thank you for your reply,I will describe the details in two days.By then I hope you could give me some suggestions.