I'm new with CYUSB and met some problems. I have made my own PCB with Altera FPGA and CY7C68013A. And I have made a mistake that I set the IFCLK pin in FPGA side as an input only pin so I have to use 68013A's internal clk.Is my understanding right that I can use it that way in synchronous slave FIFO?
I have test my code, and found when I assert SLOE and SLRD, FD[7:0] can set the first data correctly but it seems that the FIFOptr never change, data did not change and empty flag remain high.then I try it in writing, than I found the same problem ,Ican see the FPGA program function well that the FD[7:0] repeatly raising from 0 to 256, SLWR low and IFCLK in a sin curve but empty flag still low.
I also tried Asynchronous mode and met the same problem.
I have upload my code. It wouldn't be more thanksful from me that anyone could help me to solve that problems.
Solved! Go to Solution.