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USB Low-Full-High Speed Peripherals

Anonymous
Not applicable

Hello everybody

   

 

   

i am new here and this is my first post so please be patient with me.

   

 

   

I am using fx2lp (cy7c60813A) for transfering images from my camera. As a master i use FPGA Cyclone3. Now, i have setup everything and implemented (adjusted) a state machine in VHDL for bulk transfer of data. I am using the EP2,EP6 and EP8 configuration from TRM (i think it is number 4). It is valid. I should also point out that the configuration i am using worked previously just fine. Yesterday i had to re-install my system. So i deleted everything and install WinXp (32-bit) and cypress driver (3.4.5). I downloaded my FPGA configration, and any transfere i try always endups in timeout.

   

 

   

I decided to follow things with signal tap and the logic is ok. I also hooked up my scope on FullFLAG and it is always HIGH (the USB FIFO never goes full) My USB_CS, USB_WR and USB_OE pins are LOW during writing procedure while USB_RD is high. Fifo ADDRESS is set to '00' (endpoint 2). Now when i start CyConsole the device is recognized with all configurations properly initialized. In my application i use CyApi and i can read my device, configraion and enpoints with no problem. BUT TRANSFER OVER THOSE NEVER HAPPENS. I just do not understand what is happening. I also dont know what eles too try.

   

 

   

I tryed the bulkloop example provided by cypress and it works fine. My application also worked fine before i reinstalled my system. I have installed the drivers i used in previous times, but nothing works. Please tell me what can i do, what should i try what should i look for in moving ahead.

   

 

   

kind regards

   

 

   

mirza

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7 Replies
Anonymous
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Sorry just to say that my USB_OE is also HIGH not LOW.

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Anonymous
Not applicable

dear mirza

   

did you configured OUTPKTEND register in your firmware?

   

please attach your.

   

regards

   

ragers 

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Anonymous
Not applicable

Hi

   

 

   

thank you for the fast response. Please see attachement of my firmware. I am using 48MHz external clock, and i aiming for the following configuration

   

EP2 BULK IN 512k Quad Buff

   

EP6 BULK IN 512k Double Buff

   

EP8 BULK OUT 512k DoubleBuff

   

i installed cypress kit development 3.4.5 and also the uVision2 studio with keil. I can see my device in Cypress console, but not transfere occurs. I checked and double checked my WR OE CS and FLAG pins and all of them are appropriate. 

   

 

   

regards

   

 

   

mirza

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Anonymous
Not applicable

Hi

   

anyone experience any simillar problems?

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Anonymous
Not applicable

 Hello Mirza,

   

 

   

You have attached only the initialization part of firmware. Can you please attach the parts where the data is being handled. 

   

Regards,

   

Gayathri

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Anonymous
Not applicable

Hi

   

 

   

What do you mean by how is data handeled?

   

 

   

What i posted is the firmware i download to eeprom. But my data is being commited to fx2lp by external master ... a vhdl code on Cyclone3. From what i see there and the flags shown by scope, everything is ok.

   

 

   

regards

   

 

   

mirza

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Anonymous
Not applicable

 Hello Mirza,

   

 

   

As far as I understood I believe the transfers are not successful with CyConsole as well. In that case, it is not an issue with your application. Have you checked your External clock from FPGA? Is it intact? Since the interface is Synchronous, only if clocking is proper data bytes would be transferred.

   

 

   

Regards,

   

Gayatrhi

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