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USB Low-Full-High Speed Peripherals

New Contributor

We have a setup of FPGA connected to FX3 and FX3 connected to Host. One scenario is that when Host write a command to FPGA, FPGA will respond and write some data back to FX3 so host can read it. When the command is written, in logic analyzer we can see that the FPGA received the command and wrote the data in FX3 buffer, but when host read from the end point, it always blocks (timed out). Is there a way to verify that FPGA data actually arrived FX3 buffer?

On linux, the write and read has been tested with the Cypress superspeed explorer kit and works fine. The same setting with FPGA  has also been working under Windows.

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Moderator
Moderator

Hello,

Please let me know which firmware are you using.

If the FX3 is configured as Slave FIFO. Please refer to https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...

The application note mentions about the Flags that indicate the full buffer and the empty buffer. You can probe the Flags to know the status of the buffer. (refer attachment).

Please let me know if any other queries.

Regards,

Rashi

Regards,
Rashi

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4 Replies
Moderator
Moderator

Hello,

Please let me know which firmware are you using.

If the FX3 is configured as Slave FIFO. Please refer to https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...

The application note mentions about the Flags that indicate the full buffer and the empty buffer. You can probe the Flags to know the status of the buffer. (refer attachment).

Please let me know if any other queries.

Regards,

Rashi

Regards,
Rashi

View solution in original post

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New Contributor

Hi Rashi,

The FX3 is configured to use Slave Fifo Sync. Will try check the flags you mentioned and update here.

Thanks for the reply.

Frank.

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New Contributor

Checked and the FPGA is already using the flags to determine when to write data to the FX3 FIFO buffer. Compared the timing sequence on windows and they are the same. Still yet to figure out why can not read data back.

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Moderator
Moderator

Hello Frank,

For Manual DMA Channel: To know whether the data is read from the DMA buffer, you can track the Consumer event. A CONS event occurs when the buffer is read by the host.

Please set the notification for the Consumer event in the DMA channel configuration (refer attachment).

Then you can track for the this event in the DMA Callback function. Also share the USB traces (wireshark)

For AUTO DMA channel: You can probe the USB lines and share the traces . You can use wireshark (usbmon for linux) for that.

When you are writing to the DMA buffers from the FPGA, the DMA ready flags are asserted only when the DMA buffer is ready (i.e empty). If you can see the flag is asserted regularly that means the data is read and the DMA buffer is empty for the new data.

Also let me know, the number of buffers and no. of sockets that you are using in your application.

Please let me know if any  queries

Regards,

Rashi

Regards,
Rashi
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