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USB Low-Full-High Speed Peripherals

Anonymous
Not applicable

Hi All,

I am using CY7C68013A to design a USB camera, and confused by the waveform design, especially the state machine design.

The CY7C68013A is operating in GPIF mode. The data is transferred from GPIF to endpoint directly.

The hardware connection is:

  • camera pixel_clk ==> IFCLK
  • frame_valid ==> RDY0
  • line_valid ==> RDY1
  • Data[7:0] ==> Data[7:0]

The timing of camera signal is: (For simplicity only 2 lines are drawn in each frame, and 2 pixel data (clk) in each line.)

pastedImage_0.png

and I want to use the frame_valid and line_valid as the conditional term for decision points (DP).

So I designed a state machine like this:

微信图片_20180821111054.jpg

The state machine is triggered to S0, and wait for (0,0) to S1, then wait for (1,0) to S2, and wait for (1,1) to S3. In S3, the data is sampled with loop (re-execute).

When the frame_valid is deasserted, state with get back to S1, and wait for the next frame_valid asserted. The state machine will run like this forever to get the camera images frame by frame. Also the state will not get back to IDLE state forever.

For decision points S2 and S3, they have 3 branches. For example, the 3 branches of S2 are loop-back, goto-S1, goto-S3. But I found in GPIF designer, only two branches (If and else) are allowed for state transition.

Also, the logic combinations of two signals in GPIF-designer is a little confusing. I can not get 4 combinations (00, 01, 10, 11) using the given options, like this:

logic.png

My questions are:

1. How to deal with the 3-branch problem?Is this state machine a correct design for camera application using GPIF disigner? It looks that my state machine design doesn't suite for the GPIF utility.

2. In the host application end, how can I identify the different data from different frames? I am not familiar with the USB host data-receiving mechanism, and I think the data will be received packet by packet. Is there any method to separate the different frames? Is it possible that the data from different frames will be packed in one packet (for example, the end part of frame-1 and start part of frame-2)?

Any help will be greatly appreciated.

Thanks in advance.

Zheng

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1 Solution
Moderator
Moderator

Hi Zheng,

1. By adding a dummy state, you could check for one condition at each decision point. Yes, it will increase the IFCLK cycle so you could go for an alternative by only checking for frame valid signal at the decision point and using line valid as an interrupt to start reading data.

2. The header needs to be added by going into the MANUAL mode and then going back to AUTO mode after one packet with the header is committed to the host for vendor class. For UVC class, you can add an FPGA between the FX2LP and the image sensor which adds the class specific header. Please refer to the following document for more details on the implementation-USB2.0 Camera Interface Using FX2LP™ and Lattice CrossLink FPGA - KBA222479

Best Regards,

Sananya

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3 Replies
Moderator
Moderator

Hello Zheng,

1. You can add a dummy state with states S2 and S3 and check for one condition at a time in the decision point.

2.Yes, the host will receive the data in packets with the configured number of bytes. The frames can be separated by the host application if some known pattern is detected. If you are using vendor class, you can add any custom header; for UVC class, you need to add class specific payload headers. Yes, it is possible that the data in the last packet of the first frame may contain a part of the second frame if the frame length is not an exact multiple of the packet size. You need to check for the complete frame by comparing the pattern and checking for the frame length in the received bytes of data.

Best Regards,

Sananya

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Anonymous
Not applicable

Hi Sananya,

Thanks a lot for your kind reply.

1. I tried but can't figure out how to use dummy state to complete the state machine. Could you please provide some further explanation or draw a figure? Also, from the technical reference manual, the decision state will last at least one IFCLK to evaluate the condition. If a dummy state is inserted, it will take at least 2 IFCLK to get to the right condition, and this will result in the data lost, right? (During the line_valid assertion period, there are exactly N valid pixel data and the same number of IFCLKs, and all of the N data need to be sampled and transferred.)

2. Inserting a header is a method to separate the frames (for UVC or vendor class). How to insert the header? Do you mean in the firmware send a small packet to the host after each frame? If so, how to send this more data than the pixel data when the GPIF is working in Auto mode? From my understanding, in the AUTO mode, the CPU is passed-by from the data path and can not disrupt the data transaction.

3. The condition of the transition from S0 to S1 is (line_valid=00 AND frame_valid==0). How to realize this logic in the decision point configuration?

Best Wishes,

Zheng

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Moderator
Moderator

Hi Zheng,

1. By adding a dummy state, you could check for one condition at each decision point. Yes, it will increase the IFCLK cycle so you could go for an alternative by only checking for frame valid signal at the decision point and using line valid as an interrupt to start reading data.

2. The header needs to be added by going into the MANUAL mode and then going back to AUTO mode after one packet with the header is committed to the host for vendor class. For UVC class, you can add an FPGA between the FX2LP and the image sensor which adds the class specific header. Please refer to the following document for more details on the implementation-USB2.0 Camera Interface Using FX2LP™ and Lattice CrossLink FPGA - KBA222479

Best Regards,

Sananya

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