I'm designing 68013 interface with FPGA using GPIF. FPGA work as slave FIFO.
CPU could send/read bulk data in need using GPIF
CPU could send/read control data in need (could I use GPIF, too ?)
FPGA could send control data by interrupt 68013.
but I have some questions need to make clear before I could start
1. how I could send control data using CTRL_WR wave form, like program trigger CTRL_WR waveform. CTRL data is 64 bytes. I planned to use ep1 to do this.
2. as above how to trigger bulk transfer for FIFO_WR/FIFO_RD ?
other questions:
3. could I use FPGA to make 68013 get into low power mode, or how 68013 could get into low power mode to save power ?
my design is send a data block to FPGA and then sleep for a while then wakeup again to transfer.
4. and, any way to interrupt 68013 to trigger CTRL_RD wave form and report to CPU via USB ?
