FX2LP18 GPIF Hangs

[JeBo_4132831]

Hi,

I ‘ve another strange issue with my FX2LP18.

In GPIF mode used to download FPGA. I attached you my config (Cypress GPIF designer project and the associated gpif.c – slightly modified for SDCC).

Tu sum up : The EP2 is used as the Fifo Write in GPIF.

The software sent the FPGA bitstream over EP2 using XferData.

Everything works perfectly onto numerous USB port.

But, onto one USB port, the GPIF does not seems to work. Hangs … Seems it starts (I can see waveform onto FPGA side) but suddenly stops ...

Changing the size of Chunks of data being send to the FIFO EP2 seems to solve the issue.

Normally XferData sent chunks of 64ko.  If it send only chunks of 8ko it works (but it is slower ..).

But I assume there is something bad in my GPIF implementation.

The goal is send one 16 bits DATA with a control signal CS low as fast as possible.

The IFCLK clock is 48MHZ (and inverted and sent to the FPGA to respect SETUP time).

If you can look my code if it sounds OK for you …

Part of code that manage GPIF starts : (bFpgaLoadInProgress Boolean is true)

The GPIF count is set to the size (in word) of the FPGA bitstream (not visible here).

      // Handle OUT data...

      if(bFpgaLoadInProgress)               // if configuration process has started

      {

        if( GPIFTRIG & 0x80 )               // if GPIF interface IDLE

        {

          if ( ! ( EP24FIFOFLGS & 0x02 ) )  // if there's a packet in the peripheral domain for EP2

                  {

                        EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses Empty flag

                        SYNCDELAY;

                        GPIFTRIG = GPIFTRIGWR | GPIF_EP2;  // launch GPIF FIFO WRITE Transaction from EP2 FIFO

                        SYNCDELAY;

                        while( !( GPIFTRIG & 0x80 ) )      // poll GPIFTRIG.7 GPIF Done bit

                        {

                        }

                        FpgaLoadStatus = STICEX_CMD_FPGA_LOADING;                 //end of configuration

                  }

            }

      }

Thanks.

[MallikaK_22]

Hi,

Could you please let me know the peripheral device being used in the FAIL case? Is it the same peripheral being used in all cases but particularly failing only with one usb port?

Regards,

Mallika

[JeBo_4132831 · Accepted solution]

Exactly.

All the boards behave the same.  Whatever, the board used, GPIF hangs onto one USB port.

I've update my firmware (around FIFO reset/config management) following DataSheet Recommandations.

With this update, it seems to works now. Could you have a look to the changes if you can see clearly my previous error.

BEFORE (With GPIF hangs) : I've 2 procedures. Fifo_Reset() and Fifo_Config() that are called in sequence.

AFTER (Without GPIF Hangs) : Only one procedure Fifo_Reset() witht eh datasheet recommandations to clear FIFO correctly.

*** BEFORE ***

void fifo_reset()

{

  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

  SYNCDELAY;                    // see TRM section 15.14

  FIFORESET = 0x82;             // reset, FIFO 2

  SYNCDELAY;                    //

  FIFORESET = 0x84;             // reset, FIFO 4

  SYNCDELAY;                    //

  FIFORESET = 0x86;             // reset, FIFO 6

  SYNCDELAY;                    //

  FIFORESET = 0x88;             // reset, FIFO 8

  SYNCDELAY;                    //

  FIFORESET = 0x00;             // deactivate NAK-ALL

  SYNCDELAY;

}

void fifo_config()

{

  EP2FIFOCFG = 0x00; // allow core to see zero to one transition of auto out bit WORDWIDE = 1

  SYNCDELAY;

  EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops

  SYNCDELAY;

  EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops

  SYNCDELAY;

}        

*** AFTER ** REPLACED By

void fifo_reset()

{

  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

  SYNCDELAY;                    // see TRM section 15.14

  EP2FIFOCFG = 0x00;                                     // Manual Mode

  SYNCDELAY;

  FIFORESET = 0x02;             // reset, FIFO 2

  SYNCDELAY;

  FIFORESET = 0x04;             // reset, FIFO 4

  SYNCDELAY;

  OUTPKTEND = 0x82;

  SYNCDELAY;                    //

  OUTPKTEND = 0x82;

  SYNCDELAY;                    //

  OUTPKTEND = 0x82;

  SYNCDELAY;                    //

  OUTPKTEND = 0x82;

  SYNCDELAY;

  EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops

  SYNCDELAY;

  EP6FIFOCFG = 00;                                                         // Manual Mode

  SYNCDELAY;

  FIFORESET = 0x06;             // reset, FIFO 6

  SYNCDELAY;

  EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops

  SYNCDELAY;

  FIFORESET = 0x06;             // reset, FIFO 4

  SYNCDELAY;                    //

  FIFORESET = 0x08;             // reset, FIFO 8

  SYNCDELAY;                    //

  FIFORESET = 0x00;             // deactivate NAK-ALL

  SYNCDELAY;

}