USB Low-Full-High Speed Peripherals

[Anonymous]

Hi all:

   

According to the FX2LP's datasheet, the SLRD and SLWR setup and hold times are virtually impossible to meet at 48 MHz: the setup time is listed as 18.7 ns with a minimum hold time of 0 ns for SLRD, and 18.1 ns with a minimum hold time of 0 ns for SLWR. With a 20.83 ns clock, this means that the data only has 2.13 and 2.73 ns to change, over all process/voltages/temperature. For virtually any FPGA design this is essentially impossible to meet.

   

What I don't understand is that Cypress has an FPGA FX2 slave FIFO design published at AN61345:

   

http://www.cypress.com/?rID=43046

   

and that design explicitly does *not* meet the timing requirements in the datasheet. Not even particularly close: the timign report loopback/Loopback_verilog/fpga_master.twr gives:

   

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
faddr<1>    |    7.873(R)|clk_BUFGP         |   0.000|
fdata<0>    |    9.839(R)|clk_BUFGP         |   0.000|
fdata<1>    |   10.479(R)|clk_BUFGP         |   0.000|
fdata<2>    |    9.943(R)|clk_BUFGP         |   0.000|
fdata<3>    |   10.487(R)|clk_BUFGP         |   0.000|
fdata<4>    |   10.263(R)|clk_BUFGP         |   0.000|
fdata<5>    |   10.275(R)|clk_BUFGP         |   0.000|
fdata<6>    |   10.765(R)|clk_BUFGP         |   0.000|
fdata<7>    |    8.748(R)|clk_BUFGP         |   0.000|
gstate<0>   |    8.812(R)|clk_BUFGP         |   0.000|
gstate<1>   |    8.851(R)|clk_BUFGP         |   0.000|
gstate<2>   |    7.434(R)|clk_BUFGP         |   0.000|
sloe        |    8.575(R)|clk_BUFGP         |   0.000|
slrd        |    7.768(R)|clk_BUFGP         |   0.000|
slwr        |    8.581(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

   

You can see here that SLRD and SLWR have a clock-to-out time of ~8 ns, which implies, with a 20.83 ns IFCLK (which the firmware included with AN61345 uses) a setup time of ~13 ns, which is about 5ns *shorter* than the time specified in the FX2LP datasheet.

   

Does anyone have any idea what the real setup time requirements are for SLRD/SLWR for the FX2LP, or is it just impossible to run IFCLK at 48 MHz over all operating conditions?

[Anonymous]

Hi,

   

  The setup time requirement mentioned in the datasheet is based on the worst case characterization (Temperature –40 °C to +105 °C and Voltage +3.00 V to +3.60 V). Your system can run with lesser setup time but we can't ensure proper operation in all conditions.

   

Regards

   

Prajith

[Anonymous]

It's not 'my' system. I'm giving the setup times from AN61345, which is a Cypress published Application Note.

   

Are you saying that Cypress can't guarantee that their own application note example will work?

[Anonymous]

Any new information regarding this issue?

   

Is the minimum setup time for SLRD really 90% of the period for the 48MHz ifclk?

   

Barawn is very much right in his claim.

   

Regards,

   

Eyal

[sctrc_3172296]

Hello,

Is there any more clarity on this issue? To reiterate, on page 46 of this technical manual (http://www.cypress.com/file/138911/download), the setup time for SLRD is specified to be 18.7 ns with an internally sourced 48 MHz IFCLK, leaving only ~2 ns for logic and I/O buffering in an FPGA. I've seen people saying to drop the IFCLK frequency to 30 MHz to avoid the setup time violations. Is this the best known option?

Thanks!

Scott