FX2LP Slave FIFO full and empty change simultaneously

[Anonymous]

 I'm using Cypress's fx2LP slave fifo mode with fpga.

   

I have send data to fx2lp from fpga , then i check received data.
I have configured firmware 512*4 for fx2lp.
But here's problems.

When i have received the number of 2048 data, then 1 data missing.

Like the following.

0 1 2 3 4 ..255 0 1 2 3 4 ..255 0 1 2 3 4 ..255 0 1 2 3 4 ..255 
1 2 3 4 ..255 0 1 2 3 4 ..255 0 1 2 3 4 ..255 0 1 2 3 4 ..255 0
2 3 4 ..255 0 1 2 3 4 ..255 0 1 2 3 4 ..255 0 1 2 3 4 ..255 0 1
...

I don't know why this happen?
Also how can i handle of this problem?

[Anonymous]

 Is it always the same byte missing or does the behavior change from iteration to iteration?
Have you tried using a logic analyzer to capture the signaling on the bus at the point at which the missing data occurs?