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USB Low-Full-High Speed Peripherals

Anonymous
Not applicable

I am trying to establish a communication channel between FX2LP and a FPGA using the Slave FIFO. I use EP4 for this purpose. The configuration is as follows:

   

1. EP2, Auto Out, 512 bytes, bulk, triple buffered

   

2. EP4, Manual Out, 512 bytes, bulk, double buffered

   

3. EP6, Auto In, 512 bytes, bulk, triple buffered

   

4. EP8, not used.

   

The slave FIFO is 16-bit wide. I am trying to send 52 bytes of data from FX2LP to FPGA via EP4 without the involvement of the host PC. Is that possible? I have tried many ways of coding, but the Empty flag of EP4, i.e. (EP2468STAT & 0x04) or (EP24FIFOFLAGS & 0x20), was still asserted after 52 bytes of data had been written into EP4 by FX2LP.  As the FPGA had not been programmed to read data from EP4 yet, I would assume the Empty flag of EP4 would have gone off after one packat of data had been sent. So do I have to send the 52 bytes of data from the host PC?

   

Thanks for any help in advance.

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9 Replies
Anonymous
Not applicable

This is quite possibly a manifestation of invalid FIFO configuration. Please look at "EZ-USB Endpoint Buffers" section in page 33 of the TRM. You might want to use configuration 10.

   

Regards,

   

Anand

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Anonymous
Not applicable

Hi David

   

 

   

I am interested to know how you send data to EP4. Did you do it using vendor command or through the firmware?

   

The truth is that I don't know how to do it.....

   

 

   

Thanks

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Anonymous
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I followed Anand's suggestion to change EP4 to EP8. So now the configuration is :

   

1. EP2, Auto Out, 512 bytes, bulk, triple buffered
2. EP4, not used.
3. EP6, Auto In, 512 bytes, bulk, triple buffered
4. EP8, Manual Out, 512 bytes, bulk, double buffered

   

I still encountered the problem for EP8. I have done the following two tests (the external FIFO master did not read the data from the FIFO as no program had been installed on FPGA side):

   

Case 1. Sent one packet from PC to FX2LP firmware, then from FX2LP firmware to FX2LP Slave FIFO (I think this is the normal case for Slave FIFO Manual Out)   

   

(1)Initial status: (EP2468STAT & bmEP8EMPTY) was TRUE, (EP68FIFOFLGS & 0x20) was TRUE
(2)After receiving one packet from the PC host,  (EP2468STAT & bmEP8EMPTY) became FALSE, (EP68FIFOFLGS & 0x20) was still TRUE.
(3)Then FX2LP firmware executed "EP8BCH=0x02;SYNCDELAY;EP8BCL=0x0;SYNCDELAY;",  (EP2468STAT & bmEP8EMPTY) became TRUE, (EP68FIFOFLGS & 0x20) became FALSE.

   

The above behaviour was expected.

   

 

   

Case 2. Sent one packet from FX2LP to Slave FIFO without any involvement from the PC side (this is what I am trying to achieve here)
(1)Initial status: (EP2468STAT & bmEP8EMPTY) was TRUE, (EP68FIFOFLGS & 0x20) was TRUE
(2)FX2LP firmware executed "EP8BCH=0x02;SYNCDELAY;EP8BCL=0x0;SYNCDELAY;",  (EP2468STAT & bmEP8EMPTY) was TRUE, (EP68FIFOFLGS & 0x20) was still TRUE which I actually expected "FALSE" instead. If EP8FIFO remains empty, I guess I will not be able to send data to FPGA via the Slave FIFO.

   

Is the above Case 2 possible?

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Anonymous
Not applicable

I guess I can conclude that it is not possible to send a packet from the FX2LP firmware to an FPGA via the Slave FIFO. It is only possible to:

   

(1) send a packet from the host PC to an FPGA via the Slave FIFO (Auto Out mode),

   

or

   

(2) send a packet from the host PC to the FX2LP firmware and then from the FX2LP firmware to an FPGA via the Slave FIFO (Manual Out  mode).  In this case, the FX2LP firmware can edit and commit the packet, but it cannot initiate the packet. The packet must be initiated by the host PC. 

   

Both (1) and (2) requires the involvement of the host PC. 

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Anonymous
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Actually I have working firmware that does this. See fifoSendPromData(). It's the FX2LP firmware from FPGALink, which does JTAG-programming of an FPGA and subsequent slave-FIFO communication.

   
   

Normally it works with a host connected, but it does have a standalone mode where the JTAG stream and FPGA initialisation data is read from the FX2LP's EEPROM and sent to the FPGA on power-on, whether or not there is a host computer attached.

   
   

- Chris

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Anonymous
Not applicable

Incidentally, there is an error in the TRM related to this, which I reported to Cypress back in March but it has not been fixed. The example for firmware-sourced packets is given in figure 9-35, which has:

   

FIFORESET = 0x82; // advance all EP2 buffers to cpu domain

   

...whereas that line should read:

   

FIFORESET = 0x02; // advance all EP2 buffers to cpu domain

   

- Chris

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Anonymous
Not applicable

Hi Chris,

   

Please let me know the case number and the engineer to whom this issue was reported. I would like to take a look at the interaction that happened over this.

   

Regards,

   

Anand

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Anonymous
Not applicable

The service request number was 489394-411519292, March 4th 2011. I notice that Fig.9-35 in the TRM[1] is still incorrect.

   

[1] http://www.cypress.com/?docID=27095

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Anonymous
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Hi,

   

Thanks for providing the case number. I'll replicate this and make the update.

   

Thanks,

   

Anand

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