cancel
Showing results for 
Search instead for 
Did you mean: 

USB Low-Full-High Speed Peripherals

Anonymous
Not applicable
        I have a small home-made board with a CY7C68014A-56PVXC on it. It plugs into my Digilent Spartan-3 FPGA board. I configure EP2 as described in the TRM (fig.9.28) like this:   
   
CPUCS = bmCLKSPD1; // 48MHz   
SYNCDELAY();   
IFCONFIG = 0xA3; // drive IFCLK with internal 30MHz clock, use synchronous FIFOs.   
SYNCDELAY();   
REVCTL = 0x03;   
SYNCDELAY();   
EP2CFG = 0xA2;   
SYNCDELAY();   
FIFORESET = 0x80;   
SYNCDELAY();   
FIFORESET = 0x82;   
SYNCDELAY();   
FIFORESET = 0x00;   
SYNCDELAY();   
OUTPKTEND = 0x82;   
SYNCDELAY();   
OUTPKTEND = 0x82;   
SYNCDELAY();   
EP2FIFOCFG = 0x10;   
SYNCDELAY();   
   
The FPGA drives FIFOADR0 and FIFOADR1 low, and asserts SLRD and SLOE always (i.e it's always ready to accept data when data is available). I then tried a number of scenarios:   
   
1) FPGA counts IFCLK rising edges for which FLAGC says "not empty". If the host sends 1024 bytes, the FPGA shows a count of 1024. So far so good.   
   
2) FPGA calculates a 16-bit checksum of incoming data, using the same timing as in (1). If the host sends 1024 bytes, the FPGA shows a checksum consistent with it receiving 1024 bytes, comprising:   
   
256 copies of byte 0   
256 copies of byte 1   
256 copies of byte 512   
256 copies of byte 513   
   
3) FPGA counts transitions (i.e where the current byte differs from the last), using the same timing as in (1). If the host sends 1024 bytes, all zero except buf[0]=1, buf[1] = buf[512] = 2, buf[513] = 3, the FPGA displays 0x3FF.   
   
So it looks like for each 512 byte chunk, the FX2LP chip is sending the correct number of bytes to the FPGA, but it is just sending byte 0 alternating with byte 1, and throwing away everything else. It's as if the 9-bit offset which the slave FIFO uses to read from the endpoint buffer is being masked with 0x0001 somehow so rather than incrementing properly it just goes 0,1,0,1,0,1,0,1. The result is that irrespective of the number of 512-byte chunks sent, the checksum from (2) above comes out as 256 times the sum of the first pair of bytes in each chunk.   
   
So my question is, am I merely doing something silly (missing register initialisations?) or have I damaged my FX2LP in some way?   
   
I tried the exact same experiments with EP6, with exactly the same results. The other functions of the FX2LP which I have tested (e.g custom EP0 commands, EEPROM & RAM loads) appear to be working fine.   
   
Any help gratefully received!   
   
- Chris   
   
Edit: PS I can correctly read back USB bulk transfers to the FX2LP, so I suspect it's something wrong with my slave FIFO config.   
0 Likes
1 Reply
Anonymous
Not applicable
        Duh. I'm stupid. I had the FPGA driving SLWR and PKTEND low (active) when they should have been driven high. I foolishly assumed they would be ignored by the FX2 chip when doing OUT transfers.   
0 Likes